STM32f427 clock system

[ababo]

Posted on December 11, 2013 at 11:43

Hi,

Is there the possibility to achieve the maximum CPU clock speed (180MHz) with the USB clock at 48MHz??

According my calculations, to have USB clock of 48MHz I need to reduce the CPU clock to 168MHz, instead of 180MHz.

I am using an external crystal of 8MHz.

Thanks :)

#stm32f427

[chen]

Posted on December 11, 2013 at 13:00

Hi

I think (from memory - so check the data sheet for your device) some STM32 allow clocking of the CPU and USB peripheral from different/separate crystals.

This (if possible/available) should allow you to clock the STM32 at full speed and have the USB working correctly. It will however, cost you at least 1 IO pin/port.

[ababo]

Posted on December 11, 2013 at 16:32

Thanks chen chung for your reply.

I am using the USB Full Speed peripheral, that need a 48MHz clock, and the only clock source is internal, through PLL.

Only using USB high speed, an external clock must be provided to controller. 

Is this correct??

[chen]

Posted on December 11, 2013 at 17:00

Hi

''Is there the possibility to achieve the maximum CPU clock speed (180MHz) with the USB clock at 48MHz??''

Yes but you have to use multiple clock sources - ie one for clocking the CPU core and one for clocking the USB peripheral.

''the only clock source is internal, through PLL.''

Then NO

You only have 1 clock source and you have already done the calculations and found that the best the CPU core can be clocked at and still get 48MHz for USB is 168MHz

If you add another crystal to your system, and select that crystal for the clock source for the USB then Yes - you can achieve 180MHz for the CPU core.

Check to see if this is possible for your device in the data sheet!

[Tesla DeLorean]

Posted on December 11, 2013 at 17:08

The only conceivable way it would work is via the ULPI and OTG_HS_SCL

Having 180 MHz as the maximum speed seems to be a rather large and unexplained oversight. 192 MHz would have at least got you a synchronous USB clock, which is tied to a different PLL tap, but the same PLL as the CPU.