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STM32F407 VDDA-VREF+ difference
In the STM32F407 DS, ADC characteristics table has the following footnotes:
IMO 2. follows from 3. (which is a more stringent requirement); thus 2. is redundant and confusing.
JW
mƎALLEmBest answer
ST Technical Moderator
Jun 17, 2025 10:14 AM UTC
Hello,
Note 2, is related to the power-up phase while note 3 is related to the functional mode when the ADC is running.
So note 2 will be updated to mention that difference.
The proposed change:
2. When VDDA and VREF+ are supplied by independent voltage sources, during power-up phase, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V.
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