stm32f407 i2s interface sync in slave mode

[albert2]

Posted on July 17, 2015 at 10:58

Hello, I'd like to know if there is a 'magical' way to syncronize the bit stream with the channel signal in the i2s receivers. I don't have control on the external stream ( slave mode), so the serial clock is free running, and the only way I've found to use the interface is to wait for the correct time to enable it.

Perhaps there is some way to do it using the receiver but I've been unable to find it.

If this is a 'feature', perhaps it would be wise to modify the silicon on next iterations/products to allow for an automatical way to sync the receiver with the data stream.

Thank you very much.

Albert

#i2s #stm32f407 #sync

[Tesla DeLorean]

Posted on July 17, 2015 at 17:05

Isn't that the purpose of the WS signal?

[albert2]

Posted on July 20, 2015 at 08:18

Hi Clive

Yup, that's exactly the purpose of the WS signal, but the hardware implementation seems to ignore it in slave mode.

That's why i'm asking the question. It may be that i'm not implementing it well enough in the firmware (most probable), or it may be that the silicon implememntation has 'forgotten' to use it to reset the bit counter.

[HoRyong Kang]

Posted on May 07, 2018 at 07:20

Hello

I have the same problem.

The only way is to control the timing of enable I2S.

But it is not exact about 1 bit.

1 bit is very large sound because it means the sound is 2 times louder.

[albert2]

Posted on May 07, 2018 at 09:37

I answer myself. I forgot about this question pending here.

There is an easy way to synchronize the enable. The appropiate levels of the WS signal depend on the exact protocol you're using. Change as needed.

You must do the following procedure:

-disable the interface

-reset the interface

-wait for a rising edge of the ws signal

-disable interrupts

-count the clock cycles that you're using (bits) less 1, using the rising/falling edges of the clock signal

-enable the interface

-enable interrupts

this way, on the next bit clock, the interface will start with the first bit correctly clocked.

I have impolemented it this way and its working flawlessly.

Albert

[waclawek.jan]

Posted on May 07, 2018 at 09:51

I'd put the 'disable interrupts' before 'wait for a rising edge of the WS signal' (and, as you've said before, it may be 'wait for a falling edge' in some protocols).

The reason is that there's a hardware bug in the I2S module implementation in the 'classic' 'F2xx/'F4xx in that the

https://community.st.com/0D50X00009XkW2ISAV

circuit is level-sensitive instead of being properly edge-sensitive. It is described in the errata and corrected in the newer 'Fxx.

JW