STM32F407 FSMC synchronous burst AHB size?

[slqa123]

Posted on April 30, 2013 at 11:02

Hi.

I have a problem with FMSC. I want to use FSMC single synchronous burst transfer with PSRAM. The memory has a 16bit data width and i read into ref. manual that ''When the selected bank is configured in synchronous burst mode, if an AHB single-burst

 

transaction is requested, the FSMC performs a burst transaction of length 1 (if the AHB

 

transfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select

 

signal when the last data is strobed.''.

 

 

Can I choose the AHB size or it is fixed to 32bit?

 

 

Best regards Przemek

#stm32f4-fsmc-psram

[waclawek.jan]

Posted on April 30, 2013 at 13:01

It is the AHB master - usually the processor (more precisely the processor-bus interface), but also the DMA controller, for example - who determines the transfer width.

In other words, if the processor performs a halfword read or write, the transfer width is 16-bit, if a word read/write, the transfer width is 32-bit (provided the transfers go from/to apropriately aligned addresses). Normally, this directly translates to reads/writes from/to 16/32-bit variables allocated to the FSMC address space, in C.

JW

[slqa123]

Posted on April 30, 2013 at 13:26

Thanks for reply.

So when I use the forumla which return a 32bit value the AHB is 32bit, otherwise when return value is 16bit the AHB is 16bit.

Best regards Przemek