STM32F407 DMA stops working

[ken239955]

Posted on December 23, 2012 at 23:00

This problem has me stumped for the past three days. Before I get into the problem I have a few questions. When I look at the memory maps, are addresses, eg. 0x0800 0000,  in byte format or word format?

I am using STM32F407 and running IAR EWARM.

As far as I can tell, I believe the 64KB CCM is at 0x1000 0000 and the 112KB SRAM begins at 0x2000 0000. Where does the 16KB SRAM begin? (again are these byte addresses?)

My problem is I am running two DMA2 operations.

SPI1_TX on DMA2 Stream5 Channel3, memory to peripheral,

and DCMI on DMA2 Stream1 Channel1, peripheral to memory

I can get the SPI1_TX running fine. The strange thing is I have gotten both DMA requests to work on a number of occasions in the past but sometimes it fails. Now the failure is permanent.

The symptom is whenever I enable the DCMI DMA, the SPI DMA fails, DMA_S5CR EN = 0 , the error is usually transfer error and FIFO error, or AHB bus error, as if there is contention somewhere.

The DCMI requests are running at 42MHz.

I tried separating the two memory requests into the separate 112KB and 16KB blocks with no luck. I tried changing priorities by moving to different streams.

The puzzling thing is why it would work sometimes.

[Tesla DeLorean]

Posted on December 24, 2012 at 00:30

I'm not sure what you think byte/word memory is?

It's byte addressable, a 16-bit word (half-word) would access 0x08000000 and 0x08000001. Generally you're going to want to access words on even address boundaries, as this speeds access, and on older ARM designs will actually fault on odd addresses. In reality the flash memory has 64-bit word lines. The RAM is 32-bit wide, so 0x20000000 contains the first 32-bit word, 0x20000004 contains the second.

The CCM memory at 0x10000000 is closely/tightly coupled to the CPU core, and doesn't have any arbitration or contention delays because you can't DMA to it. It is also attached to the data bus, so you can't execute code out of it.

The 16K block is at 0x2001C000, on parts like the F2 all the die have 128K SRAM, but ST mark some models with less. This has resulted in some linker scripts that refer to a single linear region, and others to two discontinuous regions.

There are some errata with multiple DMA channels.

[ken239955]

Posted on December 24, 2012 at 01:20

I never thought of checking the errata. Thanks for the heads-up, Clive.

If I move over to SPI2 on DMA1 and keep the DCMI on DMA2 do you think I will get around the contention problem?

btw, thanks for the fast response. I think you saved me a lot of further headaches.

[ken239955]

Posted on December 24, 2012 at 20:40

Well I moved over to SPI2 on DMA1 and everything is dandy.

Couldn't ask for a nicer Christmas present.

Hope you get some time off for the season.

Have a Merry Christmas, Clive.