STM32F405RG IWDG Behaviour

[connect]

Hi all.

Thanks in advance for taking the time to answer - much appreciated.

Context:

STM32F405RG running 3 tasks using CMSIS_OS v2.

Using HAL.

IWDG set to 10s.

HAL_IWDG_Refresh() sprinkled throughout the 3 tasks and in idle task.

Symptoms:

IWDG resets MCU like clockwork.

Additional info:

Breakpoint in HAL_IWDG_Refresh gets hit reliably and within 1s without fail.

Watching IWDG_KR in debugger, I can't see a change to 0xAAAA despite confirming it is done and executed in code (breakpoint->stepping).

All ISR's are only used to feed threads with triggers/data using semaphores/queues - no processing or data manipulation done in ISR's.

Questions:

1.) I'm assuming the hardware is too quick to clear the KR register for the debugger to see the 0xAAAA update?

2.) Any help/advice or pointers (no pun intended) to stop regular IWDG resets appreciated.

Thanks

[TDK]

IWDG_KR is not the counter register, it is a write-only register in order to start or refresh the counter. You cannot see the actual counter. IWDG_KR always reads as 0, per the reference manual.

The IWDG keeps going during debugging, so if you're paused for a while on one statement, the chip will reset. You can change this behavior in the DBG_IWDG_STOP field.

Verify during reset that the IWDG was the cause of reset by checking RSS_CSR register. If it is, you're not refreshing it frequently enough.

[connect]

Appreciate the reply.

I missed the "read 0000h" in RM0090 p. 538.

1.) IWDG is the reset reason - hence my original post

2.) the IWDG resets every 10s like clockwork, regardless of whether the debugger is connected.

3.) HAL_IWDG_Refresh() happens reliably at sub-1s intervals, confirmed through several methods, with and without debugger attached.

[waclawek.jan]

Reduce your code so that there's nothing after enabling IWDG, just a loop with IWDG refresh and a 1s delay (i.e. no task switching, no interrupts). Still resets after 10s?

JW