stm32f401re nucleo: PLL configuration

[life758]

Posted on November 26, 2015 at 13:54

Hello everybody!

I'm trying to configure the main PLL to generate the max clock frequency (84 MHz on this board), and I'm using the HSI as PLL source.

I made some test:

- test1: HCLK=70 MHz

M=16

N=140

P=2

AHB_PR=1

APB1_PR=2

APB2_PR=1

As soon as I set the PLL output as HCLK, the uC stops working.

I mean:

- no blinking led

- random value on general purpose register

I made some test:

- test2: HCLK=35 MHz

M=16

N=140

P=2

AHB_PR=2

APB1_PR=2

APB2_PR=1

The uC works normally.

I'm missing some configuration (i.e. ART?), or the problem is the HSI and his accuracy?

Could someone help me to figure it out? Thanks!

Regards

[waclawek.jan]

Posted on November 26, 2015 at 14:17

Set FLASH latency properly.

JW

[Tesla DeLorean]

Posted on November 26, 2015 at 14:32

You also seem to be running the VCO very slowly. Doesn't it specify 192 - 432 MHz

For 84 MHz, ST runs the VCO/PLL at 336 MHz and divides that by 4 (N)

[waclawek.jan]

Posted on November 26, 2015 at 14:51

I did not check for 'F401 specifically, but doesn't the reviewed PLL range apply for them too?

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/DispForm.aspx?ID=59917

JW

[life758]

Posted on November 26, 2015 at 15:47

Thanks both of you for your input!

Regads

[life758]

Posted on November 26, 2015 at 19:10

From the RM i read this:

1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR

register

2. Check that the new number of wait states is taken into account to access the Flash

memory by reading the FLASH_ACR register

3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are

taken into account by reading the clock source status (SWS bits) or/and the AHB

prescaler value (HPRE bits), respectively, in the RCC_CFGR register

To achieve point 2 and 5 I used the istruction DSB and ISB. Is it right, or I need to check the state of bits?

************************************************************************************************************

        ; Set PLL at 70 MHz and use his output as clock sys

        LDR     r0, =0x40023800         ; RCC

        

        ldr     r1, =0x27015410         ; M=16, N=336, P=4, Q=7, HSI source PLL

        str     r1, [r0, #0x4]             ; PLLCFGR

        

        ldr     r1, [r0]                        ; RCC_CR

        orr     r1, r1, #(1 << 24)         ; PLLON=1

        str     r1, [r0]

        

        ; wait states for FLASH

        

        ldr     r2, =0x40023C00         ; FLASH register

        ldr     r3, =0x302

        ldr     r1, [r2]                    ; FLASH_ACR

        orr     r1, r1, r3                      ; ICEN=1, PRFTEN=1, 2 WS= 60<HCLK<=84

                                        

        str     r1, [r2]

        DSB

        ISB

        

        ldr     r1, =0x1002                          

        str     r1, [r0, #0x8]          ; PLL as clock sys, AHB_PR=1, APB1_PR=2, APB2_PR=1

        DSB

        ISB

***********************************************************************************************************

Regards