STM32F401RE ADC conversion when Vin > Vref+

[Bensi]

On a NUCLEO-F401RE, I am observing strange conversion values when I apply higher voltage than Vref to an ADC pin and carry out conversion on it. I would have expected the converted value to be 4095 (0fff) but in reality it is more like 3233 (0ca1) for a 5V input, so there is no way of distinguishing a genuine 2.6V input from a 5V input, for example. I get the expected values in the range 0V -> 3.3V.

The datasheet for the STM32F401re says that the GPIO pin in question (PC0) is FT and that FT pins are 5V tolerant. The manual also shows that the input is internally clamped between 0 and VDD_FT (Figure 16. Basic structure of a five-volt tolerant I/O port bit).

Is there a way to detect when Vin > Vref? And what could explain this apparently valid conversion?

Thanks.

 /

I am polling the port using the following code:

HAL_ADC_Start(&hadc1);
if (HAL_ADC_PollForConversion(&hadc1, 1) == HAL_OK)
{
 ADCValue = HAL_ADC_GetValue(&hadc1);
}
HAL_ADC_Stop(&hadc1);

I have tried in both continuous and single conversion mode. Same behaviour.

[Javier1]

Is this a custom board? what happens when you measure :

• 3,3V
• 3.31V

 How did you defined ADCValue , uint16_t?

How many precission bits did you configured the ADC with?, 12bits?

[Bensi]

It's a standard NUCLEO-F401RE board. 12bit integrated ADC.

3.3V -> 4095

3.31 -> 4095

Anywhere between 3.3V and 4.42V gives 4095, then suddenly anything above 4.43V gives 3233 (+/-20).

[gbm]

Anything above 3.7 makes the ADC non-operational, temporarily if you have luck, permanently if you are out of luck. Not the way to go.

[Bensi]

Thanks. Where does that 3.7 value come from? I'm not sure about physical damage. The datasheet says absolute max Vin is Vdd + 4.0 which is 7.3V.

[Chris1]

VAIN Max is VREF+ / VDDA.