STM32f4 Timer1 counting pulses

[MKell.2]

Hello all,

I want to count pulses with TIMER 1, because he has the fastest counting frequency.

I was able to count pulses with TIMER 2 but something in my code is missing to make it work for Timer 1: (I also checked the reference manual ...)

Maybe someone knows something that I missed.

Here is my Code:

void timer_1_pulse_counter_gpioa1_Init(void){
	RCC->AHB1ENR |= 0x01; // 1: IO port A clock enabled
	//RCC->AHB1ENR |= 0x10; // 1: IO port E clock enabled
 
	// APB1 peripheral reset register
	RCC->APB2ENR |= 0x01; // 1: enable TIM2
 
	// GPIO port mode register (GPIOx_MODER)
	GPIOA->MODER |= 0x00000008; // 10: Alternate function mode PA1 => AF mode
	GPIOA->AFR[0] |= 0x00000010; // 1000: (alternate function for TIM1/ TIm2)
	GPIOA->PUPDR |= 0x00000008; // Sets pull down resistor for PA1
 
	// CCMR!: capture/compare mode register 1
	TIM1->CCMR1 |= 0x0200; // CC2 ... , IC2 is mapped on TI1
 
	TIM1->SMCR |= 0x0007; // Bits[2:0] 111: External Clock Mode 1 - Rising edges of the selected trigger clock the counter.
	TIM1->SMCR |= 0x0050; // Bits[6:4] 110: selected Trigger: Filtered Timer Input 1 (TI1FP1)
	// 0x0050
	TIM1->ARR = 0xFFFF; // Set the timer reset on the highest possible value
 
	TIM1->CR1 |= 0x0001; //0001 Enable Timer
}

[waclawek.jan]

Which STM32f4 ?

PA1 has no TIM1 functionality. See Alternate function mapping table in datasheet.

Assuming you have a pin mapped to TIM1_CH2 in GPIO:

> TIM1->CCMR1 |= 0x0200; // CC2 ... , IC2 is mapped on TI1

This would enable TIM1_CH1 rather than TIM1_CH2; it's not what you want.

And with TIM1_CH2 you would need to select TI2FP2 in TIMx_SMCR.TS.

JW

[MKell.2]

Hey Jan,

thanks for your answer.

I own a STM32f407 board. I found this mapping table in the reference manual on side 272 (https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf ).

For me it seems like PA1 has a TIM1 functionality. Did I made here a mistake ?

(I change then to TIM1_CH2 and TI2FP2 in TIMx_SMCR.TS )

[waclawek.jan]

That's just a general drawing. The interconnection matrix is sparse. See the table in datasheet I referred to above.

JW

[MKell.2]

Ah know I got it. This is just a general reference manual. So I found the table in the Datasheet of stm32f407!

[waclawek.jan]

> RCC->APB2ENR |= 0x01; // 1: enable TIM1

Didn't you say TIM8?

Using symbols from the CMSIS-mandated device header reduces this risk.

RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;

JW

[MKell.2]

Somehow it is still not working.. Do you have another suggestion ?

void timer_8_pulse_counter_gpioa1_Init(void){
	RCC->AHB1ENR |= 0x04; // 1: IO port C clock enabled
	//RCC->AHB1ENR |= 0x10; // 1: IO port E clock enabled
 
	// APB1 peripheral reset register
	RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; // 1: enable TIM8
 
	// GPIO port mode register (GPIOx_MODER)
	GPIOC->MODER |= 0x2000; // 10: Alternate function mode PC6 => AF mode
	GPIOC->AFR[0] |= 0x3000000; // 1000: Must refer to AF3 (alternate function for TIM8)
	GPIOC->PUPDR |= 0x2000; // Sets pull down resistor for PA1
 
	// CCMR!: capture/compare mode register 1
	TIM8->CCMR1 |= 0x01; // CC1 channel is configured as input, IC1 is mapped on TI1
	// 0x0100
 
	TIM8->SMCR |= 0x0007; // Bits[2:0] 111: External Clock Mode 1 - Rising edges of the selected trigger clock the counter.
	TIM8->SMCR |= 0x0050; // Bits[6:4] 110: selected Trigger: Filtered Timer Input 1 (TI1FP1)
	// 0x0050
	TIM8->ARR = 0xFFFF; // Set the timer reset on the highest possible value
 
	TIM8->CR1 |= 0x0001; //0001 Enable Timer
}