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Andreas S.
Associate II
October 16, 2017
Question

STM32F4 SDIO 4 bit mode with CubeMX project does not work

  • October 16, 2017
  • 2 replies
  • 1490 views
Posted on October 16, 2017 at 11:58

Hi all,

I created a project in CubeMX for a STM32F429IGtx with SDIO and FatFs. Clock at 180 MHz,

The example works fine in 1 bit mode, but when I switch to 4 bit mode by adding the define 'BUS_4BITS'

it does not work and f_write returns an FR_DISK_ERROR. Have switched to DMA, seems to work only with DMA,

but not reliably.

I found an example: STM32Cube_FW_F4_V1.16.0 -> STM324x9I_EVAL that works fine in 4 bit mode.

I have tried to set the pullups in the CubeMX example, but nothing works. I can not see whats really the difference

exept a different initialization order.

Does anyone have an idea? What are the pitfalls with SDIO in 4 bit mode?

Best regards

Andreas

    This topic has been closed for replies.

    2 replies

    Zt Liu
    Senior III
    October 17, 2017
    Posted on October 17, 2017 at 11:56

    Try first disable FATFS, and check  if HAL_SDIO_Write() and HAL_SDIO_Read() are working properly.

    Lower down clock speed, check your waveform of Data pins, also check your hardware....

    Mohammad Simard
    Visitor II
    October 31, 2017
    Posted on October 31, 2017 at 08:14

    I am facing the same issue for Stm32f103re. It seems the CubeMX does not generate the correct configuration for 4 wire wide bus SD. Also manually changing of line 'hsd.Init.BusWide = SDIO_BUS_WIDE_1B;' to 'hsd.Init.BusWide = SDIO_BUS_WIDE_4B;' in 'MX_SDIO_SD_Init()' makes FATFS functions halted.

    Tesla DeLorean
    Guru
    October 31, 2017
    Posted on October 31, 2017 at 14:31

    The code initializes the card at 400 KHz and 1-bit, reads the card geometry data, and then later negotiates higher speed and wider buses.

    I'd try the SDIO examples from the SPL, and confirm if those work properly in your circuit.

    Tips, Buy me a coffee, or three.. PayPal VenmoUp vote any posts that you find helpful, it shows what's working..
    Andreas S.
    Associate II
    November 2, 2017
    Posted on November 02, 2017 at 10:40

    Hi Clive One,

    the description of the SDIOCLK clock devide factor says 'It is advised to keep the default ClockDiv value (0) to have a maximum SDIO_CK frequency of 24 MHz.'

    Maybe this is the problem, that it is too fast at the beginning? But the code in the STM324x9I_EVAL-Example works

    in the same way...

    Weird...