STM32F4 Keil ARM FPU interrupts

[John F.]

Posted on January 08, 2013 at 11:12

I want to use the STM32F4 floating point hardware FPU in my main code and in interrupt service routines. Apart from telling the compiler I'm using the FPU, do I need to do anything extra to save and restore FPU registers and status in interrupt service routines (to prevent interrupted FPU operations from being corrupted)? I assume the compiler takes care of it for me.

I have looked on the Keil website and couldn't find a clear explanation. Anybody know please?

[frankmeyer9]

Posted on January 08, 2013 at 13:35

Possibly at the source:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/index.html

[John F.]

Posted on January 08, 2013 at 17:57

Thanks for the pointer - it's useful stuff about the Cortex M4. Does anyone have practical experience with the Keil ARM tools that's relevant please?

[Tesla DeLorean]

Posted on January 08, 2013 at 18:59

You should probably look at the code generated, but I think you'd need to use the interrupt directive because the core itself doesn't stack the FPU low order registers, and the ABI likely expects them to be usable for parameters/scratch/return.

[John F.]

Posted on January 09, 2013 at 09:26

Hi Clive,

Writing in 'C', what does ''use the interrupt directive'' mean? (I have googled and searched the uVision Help - I haven't found a clear description of what happens when an FPU float operation is interrupted and the interrupt also uses the FPU for floats).

[GHITH.Abdelhamid]

Posted on January 09, 2013 at 17:46

Hi,

FP register saving modes (when FPU is enabled) is configurable in the FPU context control register (FPCCR). three mode are available : No FP registers saving, Lazy saving/restoring (only space allocation in the stack), Automatic FP registers saving/restoring.

stack frame will contain the Basic frame (cortex-m4 core register ) + Stack FPU frame 17 entries in the stack (FPSCR + S0-S15).

Lazy saving/restoring is the default mode after reset.

Below is a simple description of the execution scenario when an FPU float operation is interrupted and the interrupt also uses the FPU for floats.

In Lazy mode, the FP context is not saved (this reduces the exception latency)

If a floating point instruction is reached when lazy context save is active, the processor first retrieves the address of the reserved area from FPCAR register, saves the FP state, S0-S15 and the FPSCR, and then processes the FPU instruction.

please refer to

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/DM00046982.pdf

 for more details on Floating point unit.

[Tesla DeLorean]

Posted on January 09, 2013 at 19:26

Classically where special prologue/epilogue code is required to handle the differences between normal C function interaction, and interrupt calls that may need additional register stacking, or magic, to preserve context and return correctly.

/*
* Period Interrupt Timer (PIT) - interrupt function (every ~10 ms)
*/
__irq void PIT_Handler (void) {
TimeTick++;
*AT91C_AIC_EOICR = *AT91C_ST_SR;
}

http://www.keil.com/support/docs/29htm

http://www.keil.com/support/man/docs/ca/ca_le_irq.htm

Not sure how applicable this is. Stacking all the registers does appear to be overkill. A singular context save area would have preemption issues wouldn't it?

[John F.]

Posted on January 10, 2013 at 09:20

Thanks to ''lightning'' for the pointer to the Programming Manual. It says, ''When using floating-point routines, the Cortex-M4 processor automatically stacks the

architected floating-point state on exception entry. Figure 12 on page 42 shows the Cortex-

M4 stack frame layout when floating-point state is preserved on the stack as the result of an

interrupt or an exception.''

Agree that, ''A singular context save area would have preemption issues wouldn't it?'' so suppose that stacking all the registers is necessary. As Clive said, I should probably look at the generated code and / or see if I can get an answer out of Keil.