STM32F4 - Implementing Cortex Debug+ETM Connector (19/20-pins, 0.05")

Question

Is there any guidance or examples to follow for implementing the Cortex Debug+ETM Connector (20-pins, 0.05") on an STM32F4 board, with the connector as specified here, such that ETM trace is usable?

J-Link/J-Trace User's Guide: Connectors (keil.com)

e.g. Application Notes, or eval/disco boards that implement it so that I can see the connections in the schematic.

I see how to connect the (3) SWD and (5) TRACE pins from the micro datasheet. I'm not sure yet on things like VTref, GNDDetect, and GND/TgtPwr+Cap. Some guidance would save time and provide confidence.

So far all I've found is signal routing guidelines in section 8.4.4 "Embedded trace macrocell (ETM)" of app note AN4488 (Rev 7), "Getting started with STM32F4xxxx MCU hardware development".

Tesla DeLorean · Accepted Answer

I think Segger has some stub boards people could use to emulate or proxy for their own boards. PDQ Logic also had some, and also now look to have some Nucleo Dongles.

The Keil MCBSTM32F400 had a workable header for sure, some jumper to deal with conflicts with high order F(S)MC address bits, had to sacrfice some external memory capacity to use.

Also seem to recall the STM32429I-EVAL have ETB headers

https://www.pdqlogic.com/documents/Eval-Boards-with-ETM-Support.pdf

https://www.pdqlogic.com/documents/STM32-Nucleo-Trace-Board.pdf

https://www.keil.com/boards2/keil/mcbstm32f400/

https://keilpack.azureedge.net/content/Keil.STM32F4xx_DFP.2.15.0/MDK/Boards/Keil/MCBSTM32F400/Documentation/mcbstm32f400-schematics_V1.2.pdf

https://www.st.com/resource/en/user_manual/dm00093451-stm32429ieval-evaluation-board-for-stm32f429-mcus-stmicroelectronics.pdf