STM32F4 DMA quetion

[phuocnguyenhuu96]

Hello everyone.

I'm studying in STM32F4 and learn DMA module using Example code of St. The example show how to use DMA in Burst feature to do 3 transfers into timer register beginning at TIMx_ARR after DMA update request.

But I don't understand why address value of PeripheralbBaseAddress in the code example had define 0x04001004C. It said TIM DMAR address.

Please help me this question. Thank you so much.

[Tesla DeLorean]

Not a feature I've used, but as I understand it the DMAR address allows for TIM registers to be written that are normally too sparsely separated for normal DMA operations to step over. ie not workable with INC1, INC2, INC4 type settings.

[waclawek.jan]

Accessing the DMA registers through TIMx_DMAR allow you to perform several DMA transfers at one single trigger (e.g. after one update event, several consecutive timer registers can be changed using DMA).

JW

[phuocnguyenhuu96]

I understand the principle of DMA. One thing I don't understand here is why the base address of TIMx_DMAR was defined 0x4001004C.

[waclawek.jan]

The particular address is ST's design choice. But what probably confuses you is, that TIMx_DMAR is *not* a real register - rather, it's a "window", through which you "see" (read/write) other TIMx registers - which ones, depends on TIMx_DCR.

JW

[phuocnguyenhuu96]

Thank you so much. I have already understand.