STM32F4-Disco Strange Glitches on SPI1

[terter etuet]

Posted on May 04, 2018 at 13:07

i have a STM32F4-Disco configured SPI1 / SPI2 as slaves to observe the in- and output of an external SPI-device (done with CD4021/CD4094 shift registers) and output something on SPI1 (MISO PB4) . SCLK goes to PB13 (SPI2 SCK), PB3  (SPI1 SCK) and as external Clock to TIM2 (PA15 TIM2_ETR) to count the Pulses. Annoyingly the Clock on SPI1 Glitches, and what is very strange, it only affects SPI1... TIM2 which Counts the pulses seems ok, also SPI2...

the SCLK is connected with a short wire between PB13/PA15/PB3, tried to Terminate after with 1kOhm to VCC&Gnd, doesent help...

D4 is the SPI1-MISO with a nice glitch on the 8th pulse, D3 is SCLK, D7 is the TIM2 OC3 signal after 8 Pulses,

D5 is SPI1 MOSI....

So the Input & Output of SPI1 are scrambled....

SCLK is ca 1MHz, and the Signal integrity dosent look bad...

And when this is happening, how do i reset SPI1? Disabling / Reenabling with

__HAL_SPI_DISABLE(&hspi1);

__HAL_SPI_ENABLE(&hspi1);

doesent Help.....

Many thanks for some Pointers!

terto

[Andrei Chichak]

Posted on May 04, 2018 at 18:55

I don't understand. You've set up your Disco board as a slave and you are talking to a shift register?

A shift register is a slave. A master talks to a slave. A slave cannot talk to a slave.

If D4 is MISO, and you're talking to a shift register, then D4 is being supplied by the shift register. Look at the data sheet for the shift register for hints.

D5 being MOSI makes sense if it is being supplied by the processor, but you say the processor is a slave. Who is supplying the clock?

A

[terter etuet]

Posted on May 06, 2018 at 16:40

Thanks for your answer,

SCLK and the Data for MOSI SPI2 comes from an external controller (6502 & 6522 VIA),

the STM32F4 is just reading the the communication between Controller and the Shift registers...

the Communication is ok so far, the STM32F4 can read the data, its just the SPI1 that gets out of sync

and glitches.....