STM32F4 bxCAN FiFo Release Issues

[garyconner9]

Posted on March 13, 2014 at 21:34

Can anyone tell me if the following is normal functionality of the RFR register:

Processor clock 168 MHz

APB1 bus 42 MHz

After reading the Receive FiFo and releasing by setting RFOM1 bit to 1 in the RF1R register, we must wait until the RFOM1 is reset to 0 by the hardware before exiting the interrupt.  If we exit the interrupt while RFOM1 bit is still set, the interrupt routine is immediately re-entered and the subsequent reading of the RIR register returns a value with eroneous values.

We never saw this issue using the an STM32F3 processor at 72 MHz and APB1 bus at 36 MHz.

Thanks

[Tesla DeLorean]

Posted on March 13, 2014 at 21:42

There are certainly race conditions with the NVIC, peripherals, and the tail-chaining mechanism with buses with significant disparity in speed.

It is important to clear interrupting sources early in the handler routines, and qualify the source upon entry. This isn't unique, a lot of people first encounter it with TIM interrupts.

A read of the register prior to leaving the interrupt will force the pending write to complete, as will one of the memory fencing instructions.