STM32F373 SDADC (Sigma-Delta ADC)

[jim_wei]

Posted on March 18, 2014 at 03:12

Hello,

I am planning on using the SDADC in STM32F37x microcontroller.  The data sheets says the sampling frequency is between 500 kHz ~ 6 MHz, depending on the clock signal driving the SDADC.  The output data rate is 4.167 ksps ~ 50 ksps accordingly.  So it appears that the over sampling rate is 120.  But the data sheet never says so.  In between these two points, I can drive the SDADC with a clock signal derived from the system clock and get a output data rate of 1/120 of the frequency of the driving clock signal.  Am I correct?  Thanks for your input.

Jim

#stm32f373-sdadc

[raptorhal2]

Posted on March 18, 2014 at 14:12

The data sheet says the SDADC clock frequency is 0.5 to 6 MHz.

The output data sampling rate scales with clock frequency.

Cheers, Hal

[Amel NASRI]

Posted on March 19, 2014 at 09:59

Hi Jim,

Your analysis is correct: there is a fixed oversampling ratio 120 (input sampling frequency vs. output data rate). Input sampling frequency is the SDADC clock which you may set by software.

-Mayla-

Hello,

I am planning on using the SDADC in STM32F37x microcontroller.  The data sheets says the sampling frequency is between 500 kHz ~ 6 MHz, depending on the clock signal driving the SDADC.  The output data rate is 4.167 ksps ~ 50 ksps accordingly.  So it appears that the over sampling rate is 120.  But the data sheet never says so.  In between these two points, I can drive the SDADC with a clock signal derived from the system clock and get a output data rate of 1/120 of the frequency of the driving clock signal.  Am I correct?  Thanks for your input.

Jim

[roland2]

Posted on May 07, 2015 at 12:59

Is there some undocumented low-pass or filtering inside the SDADC?

Example: The SDADC is driven at 6MHz single channel 50ksmpls for two SDADC-units. This means every 20µs took one sample.

The ADC's became now two signals: one pwm readback and one RC-lowpass answer. The rising edge of both signals are faster than 10µs.

The ADC's now samples the signals as rising for 3 samples, this means 60µs.

That is a major fault!

How can i avoid this to get the real signal read?

[Igor Cesko]

Posted on May 25, 2015 at 11:11

In the SDADC is used Sinc filter with order 3 and oversampling 120. Therefore the rising edge is 3 samples. For continuous mode we must count with those 3 samples ''spreading'' if is used FAST mode (FAST=1).

In continuous mode with FAST=0 is data rate Fsdadc/360.

In continuous mode with FAST=1 is data rate Fsdadc/120 (but ''spreading'' of output data).