STM32F303 ; SPI Clock polarity; and interrupt not work

[placidity.master_gmail.com]

in code :

   //   Bit1 CPOL: Clock polarity

   //   1: CK to 1 when idle

   SPI2->CR1 |= 1<<1;

in fact clock is Zero when idle .

interrupt not work, src:

   //   Bit 7 TXEIE: Tx buffer empty interrupt enable

   //   0: TXE interrupt masked

   //   1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.

   SPI2->CR2 |= 1<<7 ;

   //   Bit 6 RXNEIE: RX buffer not empty interrupt enable

   //   0: RXNE interrupt masked

   //   1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.

   SPI2->CR2 |= 1<<6;

---------------

   //   52   SPI2 global

   //   0x0000 00D0

   (uint32_t) spi_2_interrupt_handler,

-------------

__attribute__((interrupt("IRQ")))

void spi_2_interrupt_handler (void)

{SPI2->DR = 0x55;}

-----------------

[Vangelis Fortounas]

Hello

If FRF bit in CR2 is set (TI mode) , polarity and phase bits are fixed and cant set from CR1 (except CRC calc)

Is NVIC SPI2 interrupt enable? If both rx and TX interrupts are enabled, inside the IRQ handler, TXE and RXNE flags must be checked before you decide to transmit or take the received data.

[placidity.master_gmail.com]

yes, TI mode was on, now it work properly.

for test i set all NVIC

NVIC->ISER[0] |= 0xFFFFFFFF;

NVIC->ISER[1] |= 0xFFFFFFFF;

NVIC->ISER[2] |= 0xFFFFFFFF;

NVIC->ISER[3] |= 0xFFFFFFFF;

NVIC->ISER[4] |= 0xFFFFFFFF;

NVIC->ISER[5] |= 0xFFFFFFFF;

NVIC->ISER[6] |= 0xFFFFFFFF;

NVIC->ISER[7] |= 0xFFFFFFFF;

The MC is not connected to other ICS. it just hangs in the air and I look at the oscilloscope what is happening at the output.

[waclawek.jan]

Read out and check the SPI registers for the interrupt enable bits, vector table content, the actual ISR in memory, and VTOR.

JW

[placidity.master_gmail.com]

everything turned out to be more fun, if you disable the usart2 interrupt, the SPI2 interrupt starts working,

although I can want to work and USART2 and SPI2

and sometimes it works all together. as if the weather on Mars depends on whether the MK will behave adequately. about frequencies above 24 MHz on the core, you can not even dream of, so much apparently did not properly separate the power supply from Stm32f3discovery. the processor stably freezes at high frequencies.

[TDK]

If your processor is "freezing" at higher frequencies, this suggests your clock settings are invalid. Possibly wait states are insufficient.

I very much doubt the results depend on the weather on Mars. Likely the answer is much more mundane and can be found within the code you're not showing us.

[placidity.master_gmail.com]

the processor starts at a high frequency, and runs normally for a few seconds. sometimes even a few minutes. and then it freezes.

the code does not make much sense to show, it is terribly simple and may even look very funny.

#define inner_sync() { __asm__("DMB\r\n"); __asm__("DSB\r\n"); __asm__("ISB\r\n"); }

   //   Bit 25 PLLRDY: PLL clock ready flag

   //   Set by hardware to indicate that the PLL is locked.

   //   0: PLL unlocked

   //   1: PLL locked

   while ( (RCC->CR) & ( 1 << 25) ) { inner_sync(); };

   //   Bit 16 HSEON: HSE clock enable

   //   Set and cleared by software.

   //   Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit

   //   cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

   //   0: HSE oscillator OFF

   //   1: HSE oscillator ON

   RCC->CR |= (uint32_t) ( 1 << 16 );

   inner_sync();

   //   The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is

   //   stable or not. At startup, the clock is not released until this bit is set by hardware.

   while ( ! ( (RCC->CR) & RCC_CR_HSERDY ) )      { inner_sync(); };

   //   Bit 19 CSSON: Clock security system enable

   //   Set and cleared by software to enable the clock security system. When CSSON is set, the

   //   clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by

   //   hardware if a HSE clock failure is detected.

   RCC->CR |= (uint32_t) ( 1 << 19 );

   inner_sync();

   //   Bits 21:18 PLLMUL: PLL multiplication factor

   //   These bits are written by software to define the PLL multiplication factor. These bits can be

   //   written only when PLL is disabled.

   //   Caution: The PLL output frequency must not exceed 72 MHz.

   //      0000: PLL input clock x 2

   //      0001: PLL input clock x 3

   //      0010: PLL input clock x 4

   //      0011: PLL input clock x 5

   //      0100: PLL input clock x 6

   //      0101: PLL input clock x 7

   //      0110: PLL input clock x 8

   //      0111: PLL input clock x 9

   //      1000: PLL input clock x 10

   //      1001: PLL input clock x 11

   //      1010: PLL input clock x 12

   //      1011: PLL input clock x 13

   //      1100: PLL input clock x 14

   //      1101: PLL input clock x 15

   //      1110: PLL input clock x 16

   //      1111: PLL input clock x 16

   RCC->CFGR |= 1<<18 ;

   inner_sync();

   //   Bit 16 PLLSRC: PLL entry clock source (in STM32F303xB/C and STM32F358xC and

   //   STM32F303x6/8 and STM32F328x8 devices)

   //   Set and cleared by software to select PLL clock source. This bit can be written only when PLL

   //   is disabled.

   //   0: HSI/2 selected as PLL input clock

   //   1: HSE/PREDIV selected as PLL input clock

   RCC->CFGR |= (uint32_t) ( 1 << 16 );    

   inner_sync();

   //   4. Enable the PLL again by setting PLLON to 1. Bit 24 PLLON: PLL enable

   RCC->CR |= (uint32_t) ( 1 << 24 ); // CHECKED

   inner_sync();

   //   Bit 25 PLLRDY: PLL clock ready flag

   //   Set by hardware to indicate that the PLL is locked.

   //   0: PLL unlocked

   //   1: PLL locked

   while ( ! ((RCC->CR) & ((uint32_t)( 1 << 25)) ) ) { inner_sync(); };

   inner_sync();

   //   Bits 1:0 SW: System clock switch

   //   00: HSI selected as system clock

   //   01: HSE selected as system clock

   //   10: PLL selected as system clock

   //   11: not allowed

   RCC->CFGR |= (uint32_t) ( 1 << 1 ); // CHECKED

   inner_sync();