STM32F302R8T6 Fanout capability

[Bill Haag]

Posted on May 10, 2017 at 18:29

Hello,

I'm using a STM32F302R8T6 in my project, and part of it's function is to be a SPI Master in a transmit only setup to a large amount of 74HC595 shift registers (45 in total).  Because I'm using a lot of shift registers, my main concern is 'can my micro handle this much load/fan-out'.  Now I've been researching fan-out, because I am not finding information about it in my micro-controllers datasheet, and I'm struggling quantifying what my actual load is going to be because of these 45 shift registers.

My high level layout is as follows: The shift registers will be placed on a circular board with a radius of ~3', the micro will be on a different 'Controller' board, they will be connected by a cable roughly 8' long.

Below are my questions plainly stated:

1) How do I quantify what my fan-out/load is using 45 74HC595s to see if my micro can handle driving this?

2) Do I need to terminate the SPI Clock line at the end of the daisy chain or will the last shift register act as a termination feature?

3) Any other advice, or gotchas you all see are appreciated.

Thanks,

Bill

[S.Ma]

Posted on May 10, 2017 at 20:44

How are the buffers connected? Like 45 x 8 bit big shift register with a single enable signal?

The spec is a bit blurr on the pad capacitance. Maybe Cj  10pF max ? so this pseudo buffer would have 450 pF load on MISO/MOSI/SCK? I would put footprint provision for a beefy mono directional buffer in case GPIO SPEED tuning is not enough.

The last buffer MISO pin should loop back to MISO of STM32 to be able to check out the bit error rate.

No termination resistor should be needed for 20Mbps SPI lanes.

Make sense?

[waclawek.jan]

Posted on May 10, 2017 at 21:24

Fan-out is really a term from the TTL era, where inputs presented significant static load (i.e. you had to sink quite a lot of current to present a valid logic 0 - the load was asymmetric, 1 required an order of magnitude less current). In CMOS, inputs present mainly capacitance, this you can find in the DS. Add them up and then look up the driving output pin's drive (current, output resistance, whichever available, Ohm's law helps to calculate one from the other), those two (plus parasitics from the traces/cabling) yield the rise/fall time of the signal. Whether that's sufficient for your particular setup or not is up to you to judge. A secondary effect from heavy capacitive loading is that the current needed to charge/discharge all that capacitance has to flow through the output transistors, so with high frequency switching this may present significant heating of them.

For shift registers, the clock  has to have a very clean active edge, else the shift register may clock more than once per edge and the output is corrupted. That's why pure clocked serial schemes are good only on a few cm (imperial: few ') within a board, and that's why there are clock recovery schemes around. You may go a bit further as long as you absolutely know what are you doing: termination is not a panacea and is mostly useless in what is basically a star. In fact, it's mostly useless at all in an uncontrolled-impedance environment, and often it helps only as an untintended slew-rate limiting device. Note that the nasty things like reflections and cross-coupling tend to get worse with frequency, but frequency here really means edges' slew rate rather than repetition/clock/pulse/whatever width/rate/whatever. So there you are with a tradeoff - a slow edge is good for low high-freq content but bad for the shift register clock. The datasheets tend to specify a maximum clock inpu rise/fall time; but even if this is obeyed but the clock is noisyn (i.e. there's high frequency content, whether it's noise, crosstalk or ringing, superimposed on the rise edge) the clock may get unreliable. The clock input in some particular makes of '595 may have some hysteresis which helps, but I've never seen such specified explicitly in the DS, so maybe it's a good idea to insert a '14 or similar to improve the clock integrity.

There's one particular gotcha with the '595 (and 74xx shift registers in general) in that contrary to SPI, they both sample and shift on the same edge. The consequence is, that if you chain them and there's a delay in the (shared thus loaded) clock between the '595 higher than the clock-to-output propagation delay in the first of them, the second will catch the newly shifted-out bit rather than the previous one as intended.

Oh, and most of the time the problems are more of the common-ground type than anything else - you really want to have a separate return for each critical signal, as close to the signal as possible, twisted if cable. Power ground and its noise is often an issue too, especially if you want to light up a gazillion of LEDs with those '595s.

JW   

[Bill Haag]

Posted on May 10, 2017 at 22:43

To

KIC8462852 EPIC204278916,

Yes, I am using one enable for all the shift registers.  All the other signals are chained together, the serial data comes in on pin 14 and leaves on pin 9 to the next shift register and so on.  OE (pin13) I mechanically toggle, SRCLR (pin10) I pull High.

As far as a buffer, I was thinking about a 74HC4050D, is there a beefier option?  I like the High speed of this but I'm not sure if this has enough umph behind it?

Thank you for the info on the termination resistor and returning on the MISO (especially this one).

To

waclawek.jan,

I have some math to do, thank you for the information, I will have more replies to come once I digest your post.

Thanks