Skip to main content
glenn0010
Associate III
May 22, 2020
Solved

STM32F3 Comp not writing to registers

  • May 22, 2020
  • 3 replies
  • 956 views

Hi All,

So I've beern trying to write to the registers of the comparator 2 but when I debug , the values of the registers don't change. This leads me to believe that I have an issue getting the clock to the peripheral.

I have a 16 MHz external XTAL which according to the RCC config below (unless I made a mistake) should give me 32 MHz at the APB2 bus which is used fro COMP 2

XTAL (16 MHz) /2 = 8 Mhz -> PLL -> PLLMMUL = 8 MHz * 9 = 72 MHz -> HCLK = 72 MHz / 2 = 36 MHz -> PCLK2 (APB2) / 1 = 36 MHz

RCC->CR |= RCC_CR_HSEON; //HSE on
	while((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY); // Waiting for HSE to be ready
	RCC->CR &= ~RCC_CR_PLLON; // Disable PLL
	while((RCC->CR & RCC_CR_PLLRDY)== RCC_CR_PLLRDY); // Wait for pll to turn off
	RCC->CFGR = RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL9 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2;//PLLSCR = HSE/2 , PLLMUL = x9 (72Mhz),AHB prescaler not devided, APB1 Clock /2 = 36MHz (Max=36MHz)
	RCC->CR |= 0x01000000; // Turn on PLL on
	while((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY); // Waiting for PLL to be ready
	FLASH->ACR |= FLASH_ACR_LATENCY_1; // Adjust flash speed for new frequency
	RCC->CFGR |= RCC_CFGR_SW_PLL; // Set PLL as system clock
 while((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL); // Wait fpr pll to be used as system clock
 RCC->CR &= ~RCC_CR_HSION; //Turning of HSI
	while((RCC->CR & RCC_CR_HSIRDY) == RCC_CR_HSIRDY); // Wait for HSI to be off

So assuming all the above is correct (Have DAC, ADC, UART, DMA phers working)

I must be missing something in the Comparator code below

// Setting the SYSCFG to enable a clock source for the comparator
	RCC->APB2RSTR |= RCC_APB2RSTR_SYSCFGRST;
	RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // Enabling Port A clock
	GPIOA->MODER |= (1<<14) | (1<<15); // Configure PA7 as analog mode
	
 
	COMP2->CSR |= COMP2_CSR_COMP2INSEL_2; //Selecting inverting input as DAC1_CH1
	COMP2->CSR |= (1<<9); //Closing the switcch to connect PA7 to comparator non invering input (window mode)
	COMP2->CSR |= (1<<10); //Selecting Timer 1 break input as the output of the comparator (NEED TO VERIFY THIS)
	COMP2->CSR |= COMP2_CSR_COMP2BLANKING_0; //Selecting timer 1 OC5 as blanking source (NEED TO VERIFY THIS)
	COMP2->CSR |= (1<<30); //Selcting output as high

I am using the STM32F302R8 so looking at the manual, it only has comp 2 available!

If anyone could shed any light on it, I'd appricieate it !

Cheers

This topic has been closed for replies.
Best answer by Tesla DeLorean

APB2RSTR is the reset register, not the enable one.

3 replies

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
May 22, 2020

APB2RSTR is the reset register, not the enable one.

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
glenn0010
glenn0010Author
Associate III
May 22, 2020

Thanks Clive! That's when the autofill get's you. Such a silly mistake! Thanks

turboscrew
Senior III
May 22, 2020

You seem to be resetting the SYSCFG-block instead of enabling it.

RCC->APB2RSTR |= RCC_APB2RSTR_SYSCFGRST;