STM32F3 ADC in differential mode

[nigel]

Posted on October 15, 2014 at 12:41

The original post was too long to process during our migration. Please click on the attachment to read the original post.

[Montassar BEN ROMDHANE_O]

Posted on October 15, 2014 at 14:56

Hi,

Please Format Code Block - Paintbrush [<>] icon, upper left of Word-in-a-box(tm) interface..

Regards,

Heisenberg.

[Tesla DeLorean]

Posted on October 15, 2014 at 17:18

No, that would appear to be a Fail!

It does not support HTML, copy and paste the code directly out of your editor/IDE

You know you can edit you own posts?

[nigel]

Posted on October 15, 2014 at 17:36

/**

  * @brief  Calibration and initialisation phases for the ADC1 in differential mode

  * @param  None

  * @retval None

  */

void calibrate_Diff_ADC1 (void)

{

uint32_t calibration_value=0;

ADC1 ->CR &= ~ADC_CR_ADVREGEN_1; //ADC1 voltage regulator enabled

ADC1 ->CR |= ADC_CR_ADVREGEN_0;

uSec_Delay(10); //ADC1 voltage regulator startup time

ADC1 ->CR &= ~ADC_CR_ADCALDIF; //single mode for calibration

ADC1 ->CR |= ADC_CR_ADCAL; //start the calibration of the ADC1

while (ADC1 ->CR & ADC_CR_ADCAL){}   //wait until calibration done

ADC1 ->CR |= ADC_CR_ADCALDIF; //differential mode for calibration

ADC1 ->CR |= ADC_CR_ADCAL; //start the calibration of the ADC1

while (ADC1 ->CR & ADC_CR_ADCAL){}   //wait until calibration done

calibration_value = ADC1 ->CALFACT;

ADC1_2 ->CCR &= ~ADC12_CCR_MULTI; //common register: independent mode

ADC1_2 ->CCR &= ~ADC12_CCR_CKMODE; //common register: asynchronous clock mode

ADC1_2 ->CCR &= ~ADC12_CCR_MDMA; //common register: direct memory access mode disabled

ADC1_2 ->CCR &= ~ADC12_CCR_DMACFG; //common register: one shot mode selected

ADC1_2 ->CCR &= ~ADC12_CCR_DELAY; //common register: 1*TADC_CLK delay between 2 sampling phases

ADC1 ->CFGR |= ADC_CFGR_CONT; //continuous conversion mode

ADC1 ->CFGR &= ~ADC_CFGR_RES;     //12-bit data resolution

ADC1 ->CFGR &= ~ADC_CFGR_EXTEN; //hardware trigger detection disabled

ADC1 ->CFGR &= ~ADC_CFGR_ALIGN;     //right data alignment

ADC1 ->CFGR &= ~ADC_CFGR_OVRMOD; //preserves ADC_DR with the old data when an overrun is detected

ADC1 ->CFGR &= ~ADC_CFGR_AUTDLY; //auto-delayed conversion mode off

ADC1 ->CFGR &= ~ADC_CFGR_JAUTO; //automatic injected group conversion disabled

ADC1 ->CFGR &= ~ADC_CFGR_DISCNUM; //1 regular channels to be converted in discontinuous mode

ADC1 ->SMPR1 |= ADC_SMPR1_SMP1_0     //601.5 ADC clock cycles for ADC1_channel1 ()

     | ADC_SMPR1_SMP1_1

     | ADC_SMPR1_SMP1_2;

ADC1 ->SMPR1 |= ADC_SMPR1_SMP2_0

     | ADC_SMPR1_SMP2_1

     | ADC_SMPR1_SMP2_2;

ADC1 ->SQR1  |= ADC_SQR1_SQ1_0; //1st conversion in regular sequence with channel1

ADC1 ->SQR1 |= ADC_SQR1_L_0; //the total number of conversions: 1

ADC1 ->DIFSEL |= ADC_DIFSEL_DIFSEL_0;//differential mode for channel1

ADC1 ->CR |= ADC_CR_ADEN; //enable ADC1

while (!ADC1 ->ISR & ADC_ISR_ADRD){} //wait for ADC1 to be ready to start conversion

ADC1 ->CR |= ADC_CR_ADSTART;         //start conversions in continuous mode

}

/**

  * @brief  Calibration and initialisation phases for the ADC2 in differential mode

  * @param  None

  * @retval None

  */

void calibrate_Diff_ADC2 (void)

{

uint32_t calibration_value=0;

ADC2 ->CR &= ~ADC_CR_ADVREGEN_1; //ADC2 voltage regulator enabled

ADC2 ->CR |= ADC_CR_ADVREGEN_0;

uSec_Delay(10); //ADC2 voltage regulator startup time

ADC2 ->CR &= ~ADC_CR_ADCALDIF; //single mode for calibration

ADC2 ->CR |= ADC_CR_ADCAL; //start the calibration of the ADC2

while (ADC2 ->CR & ADC_CR_ADCAL){}   //wait until calibration done

ADC2 ->CR |= ADC_CR_ADCALDIF; //differential mode for calibration

ADC2 ->CR |= ADC_CR_ADCAL; //start the calibration of the ADC2

while (ADC2 ->CR & ADC_CR_ADCAL){}   //wait until calibration done

calibration_value = ADC2 ->CALFACT;

ADC2 ->CFGR |= ADC_CFGR_CONT; //continuous conversion mode

ADC2 ->CFGR &= ~ADC_CFGR_RES;     //12-bit data resolution

ADC2 ->CFGR &= ~ADC_CFGR_EXTEN; //hardware trigger detection disabled

ADC2 ->CFGR &= ~ADC_CFGR_ALIGN;     //right data alignment

ADC2 ->CFGR &= ~ADC_CFGR_OVRMOD; //preserves ADC_DR with the old data when an overrun is detected

ADC2 ->CFGR &= ~ADC_CFGR_AUTDLY; //auto-delayed conversion mode off

ADC2 ->CFGR &= ~ADC_CFGR_JAUTO; //automatic injected group conversion disabled

ADC2 ->CFGR &= ~ADC_CFGR_DISCNUM; //1 regular channels to be converted in discontinuous mode

ADC2 ->SMPR1 |= ADC_SMPR1_SMP7_0 //601.5 ADC clock cycles for ADC1_channel7, clock:36MHz

     | ADC_SMPR1_SMP7_1 

     | ADC_SMPR1_SMP7_2;

ADC2 ->SMPR1 |= ADC_SMPR1_SMP8_0

     | ADC_SMPR1_SMP8_1

 | ADC_SMPR1_SMP8_2;

ADC2 ->SQR1 |= ADC_SQR1_SQ1_0 //1st conversion in regular sequence with channel7

| ADC_SQR1_SQ1_1

| ADC_SQR1_SQ1_2;

ADC2 ->SQR1 &= ~ADC_SQR1_L_0;     //the total number of conversions: 1

ADC2 ->DIFSEL|= ADC_DIFSEL_DIFSEL_6; //differential mode for channel7

ADC2 ->CR |= ADC_CR_ADEN; //enable ADC2

while (!ADC2 ->ISR & ADC_ISR_ADRD){} //wait for ADC2 to be ready to start conversion

ADC2 ->CR |= ADC_CR_ADSTART;         //start conversions in continuous mode

}