Question
STM32F2xx USB OTG_HS Host in FS mode
Posted on January 26, 2015 at 14:48
Hi,
It's already a few weeks I'm trying to bring up a solution of the USB Host via USB HS module with internal FS PHY. The same code works fine if I use OTG_FS module, once I pass to OTG_HS I'm starting to get a strange behavior which to my observation depends on some internal timing. I managed to get external device connection and exchanged a first SETUP read packet. But suddenly I found out that from time to time (about 10-20s not persistent) my OTG_HS host sporadically issues a RESET condition on the USB bus. I have seen 4ms drop on DP signal. After that I changed a bit an initialization sequence and got to the situation where OTG_HS can't properly detect device connection. It does detect but after some huge time of a 10-20min. GINTSTS also gives me a strange values that I can't explain. Below is the current initialization code. I do not use STM library but I went over library code and did exactly the same. (My initial version of the initialization works better but results in sporadic bus resets). This version has a detection problem so far./*
* IO & Clock Init
*/
if( REGS == USB_HS_REGS )
{
#ifdef CM5
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; /* Enable GPIOB Clock */
/* PB15 DM(D-), PB14 DP(D+) */
gpio_port_init( GPIOB, _IO(14)|_IO(15),
GPIO_MODE_ALT|GPIO_OUT_100M|GPIO_OUT_PP|GPIO_PULL_NO );
gpio_port_AF ( GPIOB, _IO(14)|_IO(15), AF_OTG_HS );
#endif
/* HS Module Clock Init */
RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;
}
else
{
#ifdef CM5
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; /* Enable GPIOA Clock */
/* PA11 DM(D-), PA12 DP(D+) */
gpio_port_init( GPIOA, _IO(11)|_IO(12),
GPIO_MODE_ALT|GPIO_OUT_100M|GPIO_OUT_PP|GPIO_PULL_NO );
gpio_port_AF ( GPIOA, _IO(11)|_IO(12), AF_OTG_FS_HS );
#if 0
/* PA10 ID */
gpio_init( GPIOA,10,
GPIO_MODE_IN|GPIO_OUT_100M|GPIO_OUT_OD|GPIO_PULL_UP );
gpio_AF ( GPIOA,10, AF_OTG_FS_HS );
#endif
#endif
/* FS Module Clock Init */
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
}
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; /* Used for EXT INT Control */
/* Init Global AHB Configuration Register */
REGS->GREGS.GAHBCFG = 0; /* Disable USB Int */
REGS->GREGS.GUSBCFG |= GUSBCFG_PHYSEL; /* USB 1.1 Full-Speed */
/* Core SW Reset */
usb_core_sw_reset( REGS );
/* Deactivate Power down */
REGS->GREGS.GCCFG = GCCFG_PWRDWN|GCCFG_NOVBUSSENS;
vTaskDelay( 20/portTICK_RATE_MS );
/* Force Host mode */
REGS->GREGS.GUSBCFG |= GUSBCFG_FHMOD; /* Force Host Mode */
/*
* After setting the force bit, the application must wait at least 25 ms
* before the change takes effect.
*/
vTaskDelay( 50/portTICK_RATE_MS );
/* PHY Clock */
REGS->PCGCCTL=0; /* UnGate the PHY Clock */
vTaskDelay( 20/portTICK_RATE_MS );
/* Init Host Configuration Register */
REGS->HREGS.HCFG = HCFG_FSLSPCS_48; /* FS,CLK:48MHz */
usb_host_port_reset( REGS ); /* Reset port */
#if 0
REGS->HREGS.HPRT = HPRT_PPWR; /* Poweron Host port */
vTaskDelay( 50/portTICK_RATE_MS );
#endif
/*
* Configure IRQ
*/
REGS->GREGS.GINTMSK = 0; /* Mask all general INTs */
/* Configure NVIC */
if( REGS == USB_HS_REGS )
{
NVIC_SetPriority( OTG_HS_IRQn, IRQ_PRI_USB_HS );
NVIC_EnableIRQ( OTG_HS_IRQn );
}
else
{
NVIC_SetPriority( OTG_FS_IRQn, IRQ_PRI_USB_FS );
NVIC_EnableIRQ( OTG_FS_IRQn );
}