STM32F207 DMSBMR->SR always TRUE

[calvin]

Posted on August 18, 2015 at 13:41

Hi all,

I have a problem when I want to start-up my LAN board, the example program I used is STM32F2x7_ETH_LwIP_V1.0.2, after the program is running, the software reset polling flag ((ETH->DMABMR & ETH_DMABMR_SR) will always TRUE.

I browsed many similar post and inspected the clock source on the pins ETH_RXCLK,ETH_TXCLK and there are correctly sourced with 25MHz signal.

but the flag ETH_DMABMR_SR is still TRUE, are there any other ways I can debug my board?

[waclawek.jan]

Posted on August 18, 2015 at 14:00

Have you enabled all 3 clocks in RCC?

 RCC->AHB1ENR |= 0

    | RCC_AHB1ENR_ETHMACEN

    | RCC_AHB1ENR_ETHMACTXEN

    | RCC_AHB1ENR_ETHMACRXEN

 ;

JW

[calvin]

Posted on August 19, 2015 at 05:54

Hi waclawek,

yes, as the original example code designed, the clocks RCC_ETH_MAC | RCC_ETH_TX | RCC_ETH_RX are enabled together. I describe my conditions more detail here, PHY mode is set as MII, I output a 25MHz clock from MAC to PHY_XI pin and observed the clock pins RX_CLK and TX_CLK both on PHY side and MAC side have 25MHz signal. As datasheet mentioned, RX_CLK and TX_CLK is generated by PHY, so I though PHY should be worked, the PHY I am using KSZ8721BTR.

I don't know if there is another way I could debug my board, what else conditions toggle the DMABMR->SR flag?

[waclawek.jan]

Posted on August 19, 2015 at 07:47

Besides setting all 3 clock enable bits in RCC, the only thing which comes into my mind is setting the two clock input pins to appropriate AF in GPIO_AFRL/AFRH and of course setting them to AF in GPIO_MODER.

JW

[calvin]

Posted on August 19, 2015 at 10:10

Hi, I missed some AF configurations, now the SR can return to 0 and ETH_CONFIG is completed , thank you very much for the reminding.