STM32F205 revision V has some weak GPIO port from ESD.

[CLee.5.54]

I use STM32F205ZGT6 for our product.  

In our design, PH10 and PH11 is connected external module. When external connected, the port get physical damage in only revision V. I checked that the other revision such as 1 , 2 and 3 don't have same issue.

I set PH10 and PH11 port as alternate function, Open-drain, Pullup and Active Low.

I hope to know this issue is reported or not to STM and what differ between revision V and others.

There are no mention about this issue in errata sheet. 

https://my.st.com/content/my_st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f2-series/stm32f2x5/stm32f205zg.html#resource

[Amel NASRI]

Hello @CLee.5.54​ ,

As there is no particular issue already known for STM32F205ZGT6 rev V, the problem you are reporting needs to be investigated.

So, could you please

• share the schematic of your board?
• provide the trace code of device(s) having the issue? Do all devices with the problem have the same date code?
• Is the problem seen on all rev V devices, or some of them are working properly?

Thanks,

Amel

[CLee.5.54]

Hello Amel

​

please find the information in my attachment. I put a part of schematic and internal test information in. 

Under our test that connect external module on 5 times, Defect rate is about 85% ( 13 defect / 15 samples ).

[Amel NASRI]

Hi Chikang,

The attachment is well received. It will be reviewed by our experts.

Would it be possible to complete the marking of other devices (rev V)?

Thanks,

Amel