STM32F2 LSE RTC crystal issue: Can anyone help?

[ter]

Posted on March 01, 2013 at 13:45

Hello

We use the STM32F2 for a project and have problems with the LSE crystal.

We use a Citizen CMR200T crystal (32.768kHz, CL=6pF, Farnell Nr.

1652560

) wich has a gain margin of 6.1 (according to the ST application note AN2867) and therefore is suitable.

It worked fine with STM32F205VGT6 Ref Y, now we changed to Ref X and the frequency shifts about 40ppm! There are no information about changes made from Ref Y to Ref X (despite other bootloader version).

With uC Ref Y: f=32.7679kHz (-3ppm)

With uC Ref X: f=32.7694kHz (+43ppm)

The measurement are made with the same layout, crystal and CL1/CL1 of 4.7pF, only the uC has changed. The frequency is measured at PA8 which outputs the clock trough microcontroller clock output (MCO1).

Can anyone help? How can we build a accurate RTC when the frequency shifts from uC to uC?

Regards,

Timon

#stm32f2-lse-rtc-crystal-ref-x-y

[hatem_ch]

Posted on April 05, 2013 at 21:14

Hello,

Y

ou may refer to the PIL MMS-MIC/12/7477 document published on ST web-site.

It mentions clearly that LSE’s transconductance was decreased in rev X die compared to rev Y die.

I think this is most probably the reason behind the observed drift in oscillation between two boards populated with different chips.

Ciao

[Tesla DeLorean]

Posted on April 05, 2013 at 21:32

Interestingly there is a single Google hit on this document, and it's not on ST's site. Chance of someone stumbling upon it are pretty low.

http://www.anglia.com/registration/pcn_ptn/docs/pcn/PIL%20MMS-MIC_12_7477.pdf