STM32F2, I2S and CS4344, I2S clock problem.

[marcin_kasz]

Posted on December 22, 2011 at 14:04

Hello,

I'm truing to use STM32F217 and CS4344 for my audio application.

I have problem with clock initialization.

/* Enable HSE */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

 

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }

  if (HSEStatus == (uint32_t)0x01)

  {

    /* HCLK = SYSCLK / 2*/

    RCC->CFGR |= RCC_CFGR_HPRE_DIV2;

      

    /* PCLK2 = HCLK / 1*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

    

    /* PCLK1 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

    /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

    /* Enable the main PLL */

    RCC->CR |= RCC_CR_PLLON;

    /* Wait till the main PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

   

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_1WS;

    /* Select the main PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= RCC_CFGR_SW_PLL;

    /* Wait till the main PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

    {

    }

  }

  else

  { /* If HSE fails to start-up, the application will have wrong clock

         configuration. User can add here some code to deal with this error */

  }

/******************************************************************************/

/*            I2S clock configuration (For devices Rev B and Y)               */

/******************************************************************************/

  /* PLLI2S clock used as I2S clock source */

  RCC->CFGR &= ~RCC_CFGR_I2SSRC;

  /* Configure PLLI2S */

  RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);

  /* Enable PLLI2S */

  RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);

  /* Wait till PLLI2S is ready */

  /*while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)

  {

  }*/

Program hangs on last (commented) while.

Why?

Regards,

Marcin

[Tesla DeLorean]

Posted on December 22, 2011 at 15:30

Perhaps you're using some illegitimate values for the various PLL settings, and it is consequently unable to lock.

You don't provide these values, so it's real hard to tell, but the code itself matches that which ST provides. You're not calling this function a second time, right? 

[marcin_kasz]

Posted on December 23, 2011 at 20:48

No it is called only once.

This code is generated automaticaly by stm32f2 clock excell template.

All values are verified by this template, so the only possibility is that some command is missing or ther is bud in the template.

[Tesla DeLorean]

Posted on December 24, 2011 at 01:22

That's great, but nobody is going to be able to diagnose the problem without a more complete attachment of the generated code. The pasted boiler-plate contains none of the data that makes it unique.

One of the classic problems with some of the library code has been discrepancies between what the compiler/project/code think the external oscillator (HSE) is, compared with the reality of the physical crystal placed on the board.

If you want to debug it, I'd recommend you examine the RCC registers while it is stuck in the loop and decode them vs the documentation, or other example projects that are functioning.

Also be aware that the way the library is set up, it typically calls SystemInit() to set up the clocks prior to calling main(), hence my question about it being run a second time, I'm not sure it is robust enough for that to work.