STM32F107 I2S with CubeMX

[Karim]

Posted on July 02, 2017 at 07:48

Hi, I'm trying to use I2S2 in STM32F107VC in this Configuration:

SYSCLK and HLCK: 72 MHz

I2S2 Clock (Using PLL3_VCO): 80 MHz

But in configuration tab I can't set audio frequency more than 32 KHz (i.e. 44 KHz 48 KHz and 96 KHz).

The CubeMX error is:

'With this I2S Clock (36.0 MHz), the divider value 1 is too low to obtain the desired Audio Frequency (44.0 KHz).

The I2S Clock must be higher than (45.056 MHz).'

Is it possible to implement higher audio frequencies?

Any guidance could be helpful.

Thanks

#stm32f1 #i2s

[Amel NASRI]

Posted on July 03, 2017 at 16:14

Hi

Boodaghi.Karim

‌,

I Think that you are using an old version of STM32CubeMX tool.

With last one (4.0), I don't face such issue.

Could you please update the version you are using?

-Amel

[Karim]

Posted on July 04, 2017 at 07:30

Thank you for your reply, I updated CubeMX but it seems I'm missing other thing(s).

Did you try in same configuration that I mentioned before (like pictures which I attached).

When I unchecked Master Clock Output it has no error but I want to use Master Clock Output it has error with frequencies upper than 32 KHz.

[Amel NASRI]

Posted on July 04, 2017 at 13:01

OK, I am checking. Thanks for detail.

-Amel

[Amel NASRI]

Posted on July 05, 2017 at 12:51

Hi

Boodaghi.Karim

‌,

I confirm that there is an issue withAudio frequency computation for STM32F107 device when Master clock output is enabled because usedI2S clock in calculation is wrong.

This issue is reported internally to be fixed soon. Sorry for such inconvenience

-Amel

[Karim]

Posted on July 05, 2017 at 13:30

Thank you for your effort in solving this problem.

[Mohamed Jallouli_O]

Posted on July 05, 2017 at 13:05

Hello K 270,

If you take a look at the  Refrence Manual

http://www.st.com/content/ccc/resource/technical/document/reference_manual/59/b9/ba/7f/11/af/43/d5/CD00171190.pdf/files/CD00171190.pdf/jcr:content/translations/en.CD00171190.pdf

 page 736, you'll find the I2S clock divider formula:

• When the master clock is generated (MCKOE in the SPI_I2SPR register is set):

F

S

= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide

Fs being the audio frequncy. Knowing that the minimal

I2SDIV value is 2 and the minimal value of ODD is 0 we can compute the minimal I2SxCLK  allowed for an audio frequency Fs=44 kHz.

I2SxCLK = 44000* [(16*2)*((2*2)+0)*8)] = 45.056Mhz

But, as we can see, according to your clock configuration the I2S clock= 80MHz which is obviously not 36MHz, I can tell you that there is nothing wrong with your configuration, the problem must be a CubeMx bug.

To solve that, jsut pick any audio frequncy (8kHz for example) and generate your code. Afterwards you can just change the I2S audio frequncy manually.

• Open the main.c file

• In the function: static void MX_I2S2_Init(void)

  change the value of the

  parameter

  hi2s2.Init.AudioFreq

  and make sure to respect the clock divider formula (You can go up to an audio frequency=96kHz with an I2S clock= 100MHz)

[Karim]

Posted on July 05, 2017 at 13:33

Hi Mohamed

Thank you for this complete answer.

Regards

Karim

[Imen.D]

Posted on January 12, 2018 at 16:53

Hi K 270,

I think that issue is fixed with STM32CubeMX 4.23. I don't reproduce the problem initiall described here.