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Jeroen3
Senior
February 10, 2015
Question

STM32F103G: Runtime clock changes

  • February 10, 2015
  • 6 replies
  • 1254 views
Posted on February 10, 2015 at 14:30

Currently I'm developing a battery powered application with lcd and stm32f103 (1MB).

Because a full screen update is ugly-slow on 32 MHz I'm looking for ways speed up to 72 MHz. But since this doubles the current consumption, it is not desirable to stay at 72 Mhz.

What is the best way to dynamically change the clocks?

Changing the PLL or changing the AHB dividers?

Or is is not recommended at all?

I've never used dynamic clocks before. Usually they are set & forget because it is a rather complicated habit.
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    6 replies

    Tesla DeLorean
    Guru
    February 10, 2015
    Posted on February 10, 2015 at 15:22

    Changing the APB/AHB dividers is the easiest, you'd need to adjust peripheral baud rates to compensate. You can't change the PLL on the fly, you have to switch the processor to a different source, turn off the PLL, change it's settings, turn it back on, wait for it to lock, and switch back to it.

    Your idle loop could also use WFI, rather than grinding the processor at 72 MHz. Review other low power modes.

    Current consumption is something you'll have to evaluate in your specific system, as how and what it interacts with externally are a big factor.

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    Jeroen3
    Jeroen3Author
    Senior
    February 10, 2015
    Posted on February 10, 2015 at 16:39

    I was considering reducing the APB scalers and decreasing the AHB scaler.

    Are there any caveats on runtime changing the prescalers?
    Tesla DeLorean
    Guru
    February 10, 2015
    Posted on February 10, 2015 at 17:32

    Are there any caveats on runtime changing the prescalers?

    Well they are designed not to glitch, but all peripheral clocking from them will need to have their own dividers adjusted to maintain the same rates, obviously.
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    cleonb32
    Visitor II
    March 26, 2015
    Posted on March 26, 2015 at 16:14

    Clive, 

    I am working on a CAN project that will be able to detect the CAN bit rate by reconfig the  CAN settings (Prescaler, BS1, BS2 and SJW..). My problem is: I  cannot achieve 33.3K bit rate with the current PLL setting... is it possible to achieve 33.3K at 36Mhz peripheral clock.  

    thanks, TB

    cleonb32
    Visitor II
    March 26, 2015
    Posted on March 26, 2015 at 16:23

    actually i got it working with:

    CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;

    CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq;

    CAN_InitStructure.CAN_BS2 = CAN_BS2_3tq;

    CAN_InitStructure.CAN_Prescaler = 40;

    Tesla DeLorean
    Guru
    March 26, 2015
    Posted on March 26, 2015 at 16:33

    The numbers don't really seem to jive with the clock/rates you've specified.

    What part are you using? What are the clocks, HSE,AHB,APB1,APB2, etc?

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