STM32F103 SPI->SR TXE bits always set

[ferhatyol-23]

Posted on July 18, 2017 at 10:28

Hi 

I'm using the SPI module in the STM32F103. I'have a problem. I set the SPI Module and SPI is working. But ? have a problem. 

When I load a data into the SPIx->DR register, the TXE bit is always set.  The data is being exported but the TXE bit is not low

As such, I can not control the transfer of the data.

This is my SPI Configuration codes

void SPI_Configuration(void)

{

GPIO_InitTypeDef GPIO_InitStructure;

SPI_InitTypeDef SPI_InitStructure;

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOA, &GPIO_InitStructure);

/* SPI1 Config -------------------------------------------------------------*/

SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;

SPI_InitStructure.SPI_Mode = SPI_Mode_Master;

SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;

SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;

SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;

SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;

SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;

SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;

SPI_InitStructure.SPI_CRCPolynomial = 7;

SPI_Init(SPI1, &SPI_InitStructure);

SPI_Cmd(SPI1, ENABLE);

}

What could be the problem.? Thank You

#spi #stm32f103

[Vangelis Fortounas]

Posted on July 18, 2017 at 10:37

Hello!

After you put data to DR and until DR buffer is emty TXE should be low.

After DR is empty (data went to shift registers to go to outworld) the TXE pin is SET imediately.

If you want not to have TXE interruptions you must disable TXE interruptions after you send your series of bytes .

[waclawek.jan]

Posted on July 18, 2017 at 10:38

The SPI transmitter is double-buffered. It means, that there's a holding register and a shift register - when you write into the holding register, TXE becomes zero for a short moment, but then the SPI machine transfers the data into the shift register and starts to transmit, and at that moment the holding register is empty again and TXE is set again.

If you want to check whether the data shiftout (transmission) has been completed, check the BUSY flag. Read 25.3.7  Status flags chapter in RM0008.

JW

[ferhatyol-23]

Posted on July 18, 2017 at 14:46

Thank you for the reply. I solved the problem with busy flag.