STM32F103 SPI Slave connection Bug?

[cap vor]

Posted on July 10, 2017 at 09:59

Hi,

   

   

According to the

RM0008.pdf 

, when spi in slave mode the MISO pin is transmit data, the MOSI pin is receive data.

   

But according tests and the example

STM32F10x_StdPeriph_Lib_V3.5.0\Project\STM32F10x_StdPeriph_Examples\SPI\Simplex_Interrupt

, 

that is not true.

  

The truly is MISO is receive data.

   Which is error?  document? chip?

#spi #stm32f103 #bug

[S.Ma]

Posted on July 10, 2017 at 14:05

MISO = Master mode as Input, Slave mode as Output

MOSI = Master mode as Output, Slave mode as Input

Here no confusion. UART RX/TX is more nasty and usually crossing the lines to make 2 device communicate will happen.