STM32F103: DMA1 on TIM3 and TIM4 (Upd, Ch1, Ch2/Ch3)

[wenzel]

Posted on July 14, 2014 at 12:53

Hello, I like to use DMA1 in my STM32F103 application. I need 6 timer triggered channels.

So i choosed from reference manual pg. 273:

Channel 1: TIM4_CH1

Channel 2: TIM3_CH3

Channel 3: TIM3_UP

Channel 4: TIM4_CH2

Channel 6: TIM3_CH1

Channel 7: TIM4_UP

I used the configuration of some examples. TIM3 and TIM4 are configured identical.

All DMA Channels are configured and enabled the same way.

But I only get request events from TIM4! (tested with ''transmission complete''-interrupt)

So my question is: is it possible to use 6 Channels of one DMA?

Did i missed something?

thanks in advance

#stm32f103-dma1-tim3-tim4-dma-tim

[Tesla DeLorean]

Posted on July 14, 2014 at 15:31

Not aware of anything that would preclude the use of multiple channels.

[wenzel]

Posted on July 14, 2014 at 19:04

Ok i tried with only one Timer:

I am using TIM1 on DMA1:

Channel 2: TIM1_CH1

Channel 3: TIM1_CH2

Channel 4: TIM1_CH4

Channel 5: TIM1_UP

Channel 6: TIM1_CH3

Channel 2 and 3 are not working :(

the others are fine...

It seemes that there are combinations which are not working together...

DMA_InitTypeDef DMA_InitStructure;

    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);

    DMA_Cmd(DMA1_Channel1, DISABLE);

    DMA_Cmd(DMA1_Channel2, DISABLE);

    DMA_Cmd(DMA1_Channel3, DISABLE);

    DMA_Cmd(DMA1_Channel4, DISABLE);

    DMA_Cmd(DMA1_Channel5, DISABLE);

    DMA_Cmd(DMA1_Channel6, DISABLE);

    DMA_Cmd(DMA1_Channel7, DISABLE);

    DMA_DeInit(DMA1_Channel1);

    DMA_DeInit(DMA1_Channel2);

    DMA_DeInit(DMA1_Channel3);

    DMA_DeInit(DMA1_Channel4);

    DMA_DeInit(DMA1_Channel5);

    DMA_DeInit(DMA1_Channel6);

    DMA_DeInit(DMA1_Channel7);

    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;

    DMA_InitStructure.DMA_BufferSize = 1;

    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;

    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;

    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;

    DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;

    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;

    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;

    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;

    /* DMA1 Channel5 Config TIM1_UP*/

    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & GPIOA->BSRR;

    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) & this->DmaIn[0];

    DMA_Init(DMA1_Channel5, (DMA_InitTypeDef*) &DMA_InitStructure);

    /* DMA1 Channel2 Config TIM1_CH1*/

    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & GPIOB->BSRR;

    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) & this->DmaEn[0];

    DMA_Init(DMA1_Channel2, (DMA_InitTypeDef*) &DMA_InitStructure);

    /* DMA1 Channel3 Config TIM1_CH2*/

    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & GPIOB->BSRR;

    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) & this->DmaEn[1];

    DMA_Init(DMA1_Channel3, (DMA_InitTypeDef*) &DMA_InitStructure);

    /* DMA1 Channel6 Config TIM1_CH3*/

    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & GPIOA->BSRR;

    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) & this->DmaIn[1];

    DMA_Init(DMA1_Channel6, (DMA_InitTypeDef*) &DMA_InitStructure);

    /* DMA1 Channel4 Config TIM1_CH4*/

    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & GPIOA->BSRR;

    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) & this->DmaIn[2];

    DMA_Init(DMA1_Channel4, (DMA_InitTypeDef*) &DMA_InitStructure);

    TIM_DMACmd(this->timer1->timerReg, TIM_DMA_Update, ENABLE);

    TIM_DMACmd(this->timer1->timerReg, TIM_DMA_CC1, ENABLE);

    TIM_DMACmd(this->timer1->timerReg, TIM_DMA_CC2, ENABLE);

    TIM_DMACmd(this->timer1->timerReg, TIM_DMA_CC3, ENABLE);

    TIM_DMACmd(this->timer1->timerReg, TIM_DMA_CC4, ENABLE);

    DMA_Cmd(DMA1_Channel2, ENABLE);

    DMA_Cmd(DMA1_Channel3, ENABLE);

    DMA_Cmd(DMA1_Channel4, ENABLE);

    DMA_Cmd(DMA1_Channel5, ENABLE);

    DMA_Cmd(DMA1_Channel6, ENABLE);