STM32F100RD, IrDA pulse width is 1.5uS, not 1.6uS, on 8MHz system clock

[yang_wenbo]

Posted on May 08, 2014 at 07:51

This is what I measured on scope when the STM32F100RD is working on 8MHz system clock, I tried to configure the system clock on 8MHz HSI, or to a 8MHz clock divided from 16Mhz HSE by set RCC_SYSCLK_Div2, the baud rate is 115.9Khz, but the IrDA pulse width is not exactly 3/16 or 1.63uS, instead, it's 1.5uS.

When I set the system clock to 16Mhz HSE, the pulse width is 1.68uS.

Since my application will be running on 8Mhz, I want to understand why the pulse width is shorter than the expected value from the spec.

 

I also attached my register bank for IrDA port here.

Thanks

[chen]

Posted on May 08, 2014 at 10:39

Hi

Nice measurements. However, I am not sure that trying to verify the clock freq indirectly through peripheral timings is an absolute way to measure the system clock/oscillator.

There are more direct methods like routing the HSE (external osc) to one of the IO pins.

I suspect though - that is not what you are asking/trying to do :

You want to get the IrDA working.

Just doing a couple of quick sums - I think 8Mhz system clock is not enough resolution to give you 115900 baud. That is why it works when you change the clock to 16Mhz.

The external oscillator (HSE) just provides a basis for the PLL to derive a system clock. The system clock can be a multiple derived from the HSE.

ie The external oscillator can be 8MHz but the STM32 can be clocked at a faster rate internally.

Why MUST the system clock be 8MHz?

[yang_wenbo]

Posted on May 08, 2014 at 11:22

Thanks chen_chung:

The IrDA is working with this pulse width in my system.  By IrDA physical layer spec. the IrDA should work if the width is larger than 1.41uS.

And I have the same assumption as you just said, that the 8Mhz clock might not have the enough resolution to provide an accurate 3/16 pulse from a 115900 baud( please be noted the 115900 baud is what I measured and it's fine with the 8Mhz HSI ).

I'm asking this here because if ST can confirm my assumption and that means the 1.5uS will be a consistent value due to the low system clock.