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arcann
Associate
December 11, 2013
Question

stm32f100c4 and SWD (solved)

  • December 11, 2013
  • 5 replies
  • 1088 views
Posted on December 11, 2013 at 13:39

to be migrated, sourceId: 36070:697285D7-A9CA-445D-B16C-F23BF0E3B1A3

    This topic has been closed for replies.

    5 replies

    francescatodiego
    Associate III
    December 11, 2013
    Posted on December 11, 2013 at 15:22

    I'm no expert

    but

    try to verify

    all

    of the

    jtag

    pin

    STM32 start with JTAG enabled and change to SWD when receive a clk/data command sequence.

    Check the pullup/pulldown for all  pin of jtag interface

    (

    Mine is

    just an idea

    I do not want

    to waste your time

    )

    form my stm32f4 manual

    Using serial wire and releasing the unused debug pins as GPIOs

     

    To use the serial wire DP to release some GPIOs, the user software must change the GPIO

     

    (PA15, PB3 and PB4) configuration mode in the GPIO_MODER register. This releases

     

    PA15, PB3 and PB4 which now become available as GPIOs.

     

    When debugging, the host performs the following actions:

     

    • Under system reset, all SWJ pins are assigned (JTAG-DP + SW-DP).

     

    • Under system reset, the debugger host sends the JTAG sequence to switch from the

     

    JTAG-DP to the SW-DP.

     

    • Still under system reset, the debugger sets a breakpoint on vector reset.

     

    • The system reset is released and the Core halts.

     

    • All the debug communications from this point are done using the SW-DP. The other

     

    JTAG pins can then be reassigned as GPIOs by the user software.

    I think you must connect also reset pin to interface

    arcann
    arcannAuthor
    Associate
    December 11, 2013
    Posted on December 11, 2013 at 15:29

    Will try, tnx

    Tesla DeLorean
    Guru
    December 11, 2013
    Posted on December 11, 2013 at 17:26

    Check supply actual voltage.

    Have a 10K Pull-up on PB2 (BOOT1)

    Connect NRST to interface, ideally have pull-up on that too, and SWDIO/SWCLK

    Secondary signs-of-life test via USART1 PA9/PA10 sending 0x7F @ 9600 8E1, receiving 0x79 back, with BOOT0 pulled high.

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    arcann
    arcannAuthor
    Associate
    December 11, 2013
    Posted on December 11, 2013 at 21:33

    Good evening, mates!

    Tnx for your advices, it may be helpful in other time.. but this problem solved from another way.

    I'd say, very unexpected way.

    I'm update firmware of stm32vldiscovery ST-Link module from 1.10 to 1.12 and all gets ok.

    I hope this solution can help anyone else 

    Tesla DeLorean
    Guru
    December 11, 2013
    Posted on December 11, 2013 at 22:32

    Thanks for the update, I'd kind of discounted that because it was another Value Line part.

    Tips, Buy me a coffee, or three.. PayPal VenmoUp vote any posts that you find helpful, it shows what's working..