Solved
STM32F0xx Hardfault through PLL misconfiguration?
Hi,
we have a strange behaviour which could be resolved by changing clock configuration, but we cannot explain why the errors occured in the first place. Perhaps some of you have any idea why the following happened:
- random hardfault during runtime after 2min to several hours
- only on a few of thousands of devices, all from a limited production batch over half a year
The "error" was in the SetSysClock function which was as following:
static void SetSysClock(void)
{
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK / 1 */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK / 1 */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL2);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
}and basically does two things wrong:
- uses PLL with HSI to achieve 8MHz clock, where PLL is not needed and can be skipped totally (dividing HSI by 2 and then multiplying it with 2)
- uses wait states while for 8MHz none are required
Still even with this configuration the core should run normal. If we remove the FLASH_ACR_LATENCY and PLL configuration, everything works fine and the error is gone.
Anyone with any ideas?
Regards,
Patrick
