STM32F091 Flash erase, how long does it take busy to go active?

[Oliver Sedlacek]

I'm working on a bootloader which needs to erase and program the Flash. The erase seems to be 'working' but I have a suspicion that I'm not waiting long enough for the 'Busy' bit to go active after setting the 'Start' bit. The reference manual says I need to poll for 'Busy' to go active in the pseudo code, but leaves it to the user to code a timeout. Can anyone give me the timings for the Flash status register as I can't find it in the data sheet?

[Uwe Bonnes]

The recent datasheet gives timing in 6.3.10. The steps to take are given in rm0091, chapter 3.

[Oliver Sedlacek]

The data sheet 6.3.10 only gives the Flash memory timings, not the FLASH peripheral SR and CR register timings. The reference manual includes the code snippet below in A.2.3 but when I try it the SR says the erase is done immediately.

/* (1) Set the PER bit in the FLASH_CR register to enable page erasing */
/* (2) Program the FLASH_AR register to select a page to erase */
/* (3) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (4) Wait until the BSY bit is reset in the FLASH_SR register */
/* (5) Check the EOP flag in the FLASH_SR register */
/* (6) Clear EOP flag by software by writing EOP at 1 */
/* (7) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_PER; /* (1) */
FLASH->AR = page_addr; /* (2) */
FLASH->CR |= FLASH_CR_STRT; /* (3) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (5) */
{
FLASH->SR = FLASH_SR_EOP; /* (6)*/
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PER; /* (7) */

[waclawek.jan]

Hi Oliver,

is this problem still persisting?

JW

[Oliver Sedlacek]

Now only of academic interest, not holding me up.

[Piranha]

RM0091 section 3.2.2, Flash memory erase, Page Erase (page 60):

The software should start checking if the BSY bit equals “0�? at least one CPU cycle after setting the STRT bit.

Add one dummy read of FLASH_CR or FLASH_SR register before waiting on BSY bit and that will be more than enough. An example of universal dummy read implementation can be found in my post there:

https://community.st.com/s/question/0D50X0000Bmnksg/stm32f446ze-doesnt-enter-in-standby-mode

[Oliver Sedlacek]

Thanks. I got myself confused and didn't trust the RM but it's correct.