STM32F071V8 ADC ADC_IN17 (VREFINT) measurement errors

[Sandhya Sharma]

Posted on February 14, 2018 at 14:33

Hi all,

We are using a STM32F071V8 MCU in our project. I am polling the ADC to read the data and have followed the following procedure to initialize the ADC:

1. enable clock to respective GPIOs

2. Initialize GPIO pins as Analog Inputs

3. Turn on HSI14MHZ clock

4. enable clock going to ADC

5. reset ADC

6. begin ADC calibration

7. wait for calibration to finish 

8. enable the ADC

9. enable the VBAT divider and temperature sensor

10. Configure the sampling time

11. Configure ADC_CFGR1  register for settings - 12 bit resolution; Analog WDT disabled; Sinlge conversion mode

12. Configure ADC_CFGR2  register for settings - ADCCLK (Asynchronous clock mode)

13. wait for ADC to finish starting up

I was trying to determine the value of VDDA by using the formula below: 

VDDA = 3.3 V x VREFINT_CAL / VREFINT_DATA

The

VREFINT_CAL value read is 1519. Upon reading the ADC_DR register after calibration I found the calibration factor to be 0x42. 

When I poll for the data on the ADC_IN17 channel it varies drastically with respect to the sampling time.

Please find the results below: 

SMP[2:0] = 000: 1.5 ADC clock cycles ; ADC counts = 1891; VDDA = 2.26V 

                   001: 7.5 ADC clock cycles ; ADC counts = 1657; VDDA = 3.06V

                   010: 13.5 ADC clock cycles;

ADC counts = 1383; VDDA = 3.6V (Worse!)

                   011: 28.5 ADC clock cycles;

ADC counts = 1510; VDDA = 3.319V 

                   Remains almost same for higher sampling time.

Could you please help me draw an inference here?

Thanks in advance. 

#stm32f0-adc-vrefinit

[Sandhya Sharma]

Posted on February 14, 2018 at 15:10

The data sheet mentions the minimum sampling time to read the Vrefinit as 4usec , so that explains the behavior probably. 

[T J]

Posted on February 15, 2018 at 03:44

are you in a hurry ?

reduce the adc clock rate and don't use the fastest sampling rate..

it will settle down.

put a scope across Vdd/Vss look for your noise. looking from 20Mhz down to 10khz.

then similarly across Vdda / Vssa

then scope from Vssa to any analog input pin.

what bypassing do you have on the Vdda/Vssa pins ? 

I use 1uF and 0.1uF on all Vdd/Vss pins.

[Sandhya Sharma]

Posted on February 15, 2018 at 08:24

Hi TJ,

Thank you for the response. I will probe the Vdd/Vss for noise. 

I need to sample the ADC data as quickly and efficiently I can. I have 0.1 and 10 uF caps on the Vdd/Vss pins. 

[AvaTar]

Posted on February 15, 2018 at 09:11

Pulling some things together:

9. enable the VBAT divider and temperature sensor

...

I need to sample the ADC data as quickly and efficiently I can.

Not sure if both statements belong together, but high sampling rates make no sense for this two parameters, as they are changing quite slow.

Even rates of one sample per second would be fine IMHO.

And don't forget to configure the sampling time according to your input impedances, else you get a 'drag effect', and increased noise.

[Sandhya Sharma]

Posted on February 16, 2018 at 16:28

Thank you for the explanation. It was very helpful. I had an additional query. I am currently reading 6 analog channels using the DMA one shot mode. The DISCEN=0  and CONT= 0(I am sampling multiple channels in single conversion mode) .The data sheet says that, after the scan sequence the DMA is stopped. Does that mean that the DMAEN bit of the ADC_CFGR1 register becomes 0 or the EN bit of the DMA_CCR1 goes 0? However, I don't find any one of them go 0 in the watch window.