Question
STM32F042F6T IWDG doesn't reset (but sets RCC->CSR flag?)
Posted on November 21, 2016 at 03:36
Hi there,
I just came across a problem and was wondering whether I'm doing something wrong here (haven't used IWDG yet). Scenario: I'm starting the IWDG and after the timeout it sets the CSR flag as expected - but it doesn't actually reset the core?! Option bytes are set to SW start, as per default. So it seems the iwdg is running but it just can't reset the core. After a manual reset the leds flash as per check routine and the CSR bit is cleared. But no reset ever happens from the iwdg. Neither in debug mode, nor in free running. BUT If I uncomment the last line, the flag is never set. So the iwdg gets reset properly. It only can't do the actual reset as it seems. Is there some bit that needs to be set to allow the iwdg to do that? I would expect that to be set during the iwdg init, though. Any help is much appreciated, thanks! Here's the code (CubeMX HAL): iwdg.c:void
MX_IWDG_Init(
void
)
{
hiwdg.Instance = IWDG;
hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
// 40kHz LSI / 4 = 10KHz
hiwdg.Init.Window = IWDG_WINDOW_DISABLE;
hiwdg.Init.Reload = 2000;
// 1/10000 * 2000 = 0.2s timeout
if
(HAL_IWDG_Init(&hiwdg) != HAL_OK)
{
Error_Handler();
}
}int
main(
void
) {
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration----------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_CAN_Init();
MX_IWDG_Init();
MX_TIM2_Init();
MX_ADC_Init();
MX_CRC_Init();
/**
* check for IWDG reset occurrence
*/
if
(__HAL_RCC_GET_FLAG(RCC_FLAG_IWDGRST) != RESET)
{
// flash x times
for
(
int
i = 0; i < 20; i++) {
LEDs_on();
HAL_Delay(50);
LEDs_off();
HAL_Delay(50);
}
/* Clear reset flags */
__HAL_RCC_CLEAR_RESET_FLAGS();
}
/*
* Start independent watchdog to auto-restart the mcu in case of a hickup
*/
HAL_IWDG_Start(&hiwdg);
/*
* Start listening to CAN
*/
HAL_CAN_Receive_IT(&hcan, CAN_FilterFIFO0);
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while
(1) {
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
// rest is interrupt controlled
// reload the independent watchdog to prevent system reset
HAL_Delay(150);
// HAL_IWDG_Refresh(&hiwdg); // test IWDG reset
}
}