STM32F030 ADC external resistor

[martincho]

I need to measure a signal that arrives on the board through a 100K resistor. I am trying to avoid having to add an operational amplifier to buffer it before the ADC input. I could use a bit of help understanding what the data sheet says about the ADC.

I only need 10 bits and the measurements do not have to happen quickly. The max Ts of 239.5 cycles (17.1 us) would be fine. In fact, I can wait longer if necessary.

On page 67, Table 50 I see Rain listed as "External input impedance" and a max value of 50K.

Applying equation 1, on page 68, to a 10 bit resolution with the maximum Ts of 239.5 cycles gives me a maximum external input resistance of 256K. This, of course, is more than my 100K, so it would seem I'm OK.

Table 51 on page 69 has "NA" listed for Ts of 71.5 and 239.5. There's no explanation as to why other than, as I see it, table 50 stating that the maximum external resistance is 50K.

What left me wondering is that this number seems to correspond to a 1/4 LSB maximum error at 12 bits.

Am I correct in assuming I can actually use a 100K resistor if all I want is 10 bits?

Also, on page 70, note 2 under Figure 24, it says the ADC operating frequency can be reduced. I looked in MX and can't seem to find a way to do this.

Thank you.

[waclawek.jan]

> I need to measure a signal that arrives on the board through a 100K resistor.

> I only need 10 bits

10 bits is far from being "only".

10 bits is 1024 bins, so any 0.1% error source matters. That would imply input impedance 100MOhm. That's start to be challenging even on the PCB.

Or, in other perspective, it would mean leakage in the order of 10nA and below. That's how much the IO structures on the chip leak, and that's the reason for minimum required source impedance, not the RC time constant on the sampling capacitor.

JW

[martincho]

Can you explain how you reached the conclusion that 10 bits requires 100 MOhm (1E8) input impedance? I am not sure I follow.

Thanks for making the connection between leakage current and the external resistor specification, I didn't think of that.

Here's something that isn't clear to me: Is the quoted leakage current for the case of the ADC having the internal capacitor connected to the input pin? I am trying to understand if input leakage changes significantly on a pin that is not being sampled. Not sure I see this anywhere in the data sheet.

BTW, I don't need to take measurements any faster than perhaps once per second. In that sense I have a lot of flexibility. I might even be able to go down to 8 bits.

Thanks.

[waclawek.jan]

> Can you explain how you reached the conclusion that 10 bits requires 100 MOhm (1E8) input impedance?

Your 100kOhm and the 100MOhm leakage form a resistive divider from your ideal signal voltage source; the sampling capacitor is across the 100MOhm leakage (it's probably more "normal" to say that the leakage is across the capacitor, but it's the same, they are in parallel). Thus, 1/1000 (okay, 1/1001, but that doesn't matter for the principle) of input voltage remains on the 100kOhm resistor and the sampling capacitor sees only 999/1000 of the input voltage. For full scale, that's 1 bin of the 1024 of the 10-bit ADC.

> Here's something that isn't clear to me: Is the quoted leakage current for the case of the ADC having the internal capacitor connected to the input pin?

Probably not. I'd say the leakage is dominated by the protection structures. But I'm not ST. And I'm sure ST will happily come to the rescue with data, would you present significant buying power, as expressed in M$. Until then, ST's (and every other semiconductor manufacturer's ) best interest is to yield publicly as little information as absolutely necessary to remain competitive.

> BTW, I don't need to take measurements any faster than perhaps once per second.

I don't see how can that help with the leakage problem.

But, as Uwe pointed out, the leakage is probably significantly temperature dependent so you if you don't need guarantees and you stay at room temperature...

JW

PS. Have you tried to achieve the "only 10 bit" precision with a low-impedance source, yet?

[Uwe Bonnes]

Put a big capacitor in parallel to the Input ( C par > (1 << 10) * Csample) and sample so slow that the RC recharging is better than (1 - (1 << 10)). Bias at room temperature is probably much smaller than Jan predicts, but test limit in the datasheet apply.

[Ozone]

> I only need 10 bits and the measurements do not have to happen quickly.

I don't think that reducing resolution is helping you with imput impedance.

> The max Ts of 239.5 cycles (17.1 us) would be fine. In fact, I can wait longer if necessary.

As a first (and usually sufficient) approximation, the ADC is a RC element.

Your input source must be able to charge the S&H capacitor through the input impedance in the given sampling time.

If not, you get distortions, "drag-over" effects and incorrect values.

You can do the calculation yourself.

[martincho]

> I don't think that reducing resolution is helping you with input impedance.

Unless I am reading it wrong page 68 of the data sheet, equation 1, seems to indicate this is a factor:

On this next page, Table 51, they provide results for the 12 bit case:

 

I reproduced this table and calculated the values for 10 and 8 bits and lowered the ADC clock to 12 MHz (the /4 I can use). According to this, yes, sampling rate and ADC width do give you the ability to use a larger Rin. However, the overriding fact seems to be that we are limited to 50K due mostly to leakage.

 

At this point I am thinking of a version of Uwe's external capacitor suggestion. I can't load the input too much because I am effectively measuring in the middle of the voltage divider for an op amp's feedback loop. I was trying to get clever and save a few components on this multi-channel design. It's looking like I won't be able to do this. My inputs can easily survive a quick low impedance sample. I could setup a FET-gated sample-and-hold using a larger capacitor to then drive the ADC input from a low impedance source. At some point the cost, complexity and errors introduced by such a solution is likely to just drive adding another set of op amps in unity gain and get on with it.

Thanks.

[martincho]

This application note from Texas Instruments covers the subject well and arrives at the same equation found on page 68 of the STM32F030 data sheet:

https://www.ti.com/lit/an/slaa036/slaa036.pdf

They don't really speak of input leakage current but it seems sensible to assume this is a factor.