STM32F0 TIMx gate mode channel selection

[Daniel Correia]

Posted on May 02, 2018 at 20:48

I'm using the gate mode TIM scheme as detailed in the reference manual:

TIM3->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1)*/

TIM3->CCER |= TIM_CCER_CC1P; /* (2) */

TIM3->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */

TIM3->PSC = 0; /* (4) */

TIM3->ARR = 65000;

TIM3->CR1 |= TIM_CR1_CEN; /* (5) */

This works perfectly for channel 1.

Now I'm trying to dynamically change channels, and I can't seem to wrap my head around the masks.

I've tried a number of register masks, like

TIM3->CCMR1 |= TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_1; /* (1)*/

and 

TIM3->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1)*/

But I haven't been able to get the input to switch..sorry for such a stupid question, I'm sure there's something in the reference manual that I'm missing.

#input-capture-mode #tim #timer-gated #tim-pwm

[waclawek.jan]

Posted on May 03, 2018 at 21:29

// missing defines - ST still refuses to put them where they belong, to the CMSIS-mandated header
// trigger (TRGI) source
#define TIM_SMCR_TS__ITR0 0 // slave -- see below for individual timers
#define TIM_SMCR_TS__ITR1 1
#define TIM_SMCR_TS__ITR2 2
#define TIM_SMCR_TS__ITR3 3
#define TIM_SMCR_TS__TI1F_ED 4 // both edges on CH1 input
#define TIM_SMCR_TS__TI1FP1 5 // TI1FP1 with the same polarity as if CH1 used for capturing in CC1
#define TIM_SMCR_TS__TI2FP2 6 // TI2FP2 with the same polarity as if CH2 used for capturing in CC2
#define TIM_SMCR_TS__ETRF 7 // external trigger input
#define TIM_SMCR_SMS__NO 0 // slave mode disabled, timer clocked from internal clock
#define TIM_SMCR_SMS__ENCODER1 1 // TI2FP2=CLK, TI1FP1=dir
#define TIM_SMCR_SMS__ENCODER2 2 // TI1FP1=CLK, TI2FP2=dir
#define TIM_SMCR_SMS__ENCODER3 3 // quad mode, counts on both signal's edges
#define TIM_SMCR_SMS__RESET 4
#define TIM_SMCR_SMS__GATED 5
#define TIM_SMCR_SMS__TRIGGER 6
#define TIM_SMCR_SMS__EXT_CLK_1 7
 
// note - CCyS bits are writable only if TIMx_CCER.CCyE = 0
#define TIM_CCMR_CCS__OUTPUT 0 // CC unit in compare mode
#define TIM_CCMR_CCS__INPUT_TI1 1 // CC unit in capture mode, input from 'own' pin (i.e. TI1 for CC1, TI2 for CC2, TI3 for CC3, TI4 for CC4)
#define TIM_CCMR_CCS__INPUT_TI2 2 // CC unit in capture mode, input from 'neighbour's' pin (i.e. TI2 for CC1, TI1 for CC2, TI4 for CC3, TI3 for CC4)
#define TIM_CCMR_CCS__INPUT_TRC 3 // CC unit in capture mode, input from TRGI (this works only if internal trigger input is used, i.e. from other timer)

#define AND &
#define OR |
#define SHL <<
 
TIM3->CCMR1 = 0
 OR (TIM_CCMR_CCS__INPUT_TI1 SHL TIM_CCMR1_CC1S_Pos) // CH1 'capture' mode (to turn the pin to input -- as opposite to compare=output mode)
 OR (TIM_CCMR_CCS__INPUT_TI1 SHL TIM_CCMR1_CC2S_Pos) // do the same with CH2, in preparation of the switching below
;
TIM3->CCER = 0
 OR TIM_CCER_CC1P // CH1 inverted
 // there's no need to enable capture, slave mode taps out signal before the capture circuit
;
TIM3->SMCR = 0
 OR (TIM_SMCR_TS__TI1FP1 SHL TIM_SMCR_TS_Pos) // TRGI comes from filtered CH1
 OR (TIM_SMCR_SMS__GATED SHL TIM_SMCR_SMS_Pos) // it appears that the TRGI DMA is not active unless a 'real trigger' happens (?)
;
TIM3->PSC = 0;
TIM3->ARR = 65000;
TIM3->CR1 = 0
 OR TIM_CR1_CEN
;
// now switching channels - we have already set CH2 to input, so it's enough now switch the routing in the slave-mode controller
TIM3->SMCR = (TIM3->SMCR AND ~TIM_SMCR_TS_Msk)
 OR (TIM_SMCR_TS__TI2FP2 SHL TIM_SMCR_TS_Pos)
;

JW

[Daniel Correia]

Posted on May 04, 2018 at 00:10

Thank you very much!

...heh, it's pretty funny how far off base I was.

[waclawek.jan]

Posted on May 04, 2018 at 00:15

Note, that you can use only CH1 or CH2 as input to the slave-mode controller (i.e. not CH3 nor CH4).

JW