STM32 Timer OPM question

[Uwe Bonnes]

Hello,

is there any way to achieve this timer OPM behavior?

• Arm timer ->Output is inactive
• Start timer-> Output gets avtive
• Compare register triggers -> Output gets inactive
• ARR triggers: Timer stops _and_ Output stays inactive

At the moment, I force the Output active before timer start and after start I set PWM mode 2 "Set channel 1 to inactive level on match. ". However interrups between force and timer start can disturb timing an so I need to globally disable interrupts for some time. I would like to get rid of that disable IRQ.

Thanks

[waclawek.jan]

You might want to have a look at the Fast enable (CCMR.OCxFE). The actual working might be confusing, if I am not mistaken, the resulting pulse length is the whole cycle i.e. governed by ARR.

JW

[Uwe Bonnes]

The pulseform I want to generate is for the One-wire primitives, as used for the DS18B20. After setting the output inavtive, another timer channel must wait for the rising edge of the response and then guard all with siome timeout. So a full ARR active cycle is not what I want. Otherwise I also do not understand the working of "fast enable" from the explications in the reference manual. B.t.w, if the timer would gate the Output with CEN, everything would be fine...

[waclawek.jan]

I'm now lost.

Can you please draw a timing diagram of what do you want to achieve, perhaps indicating also the stimuli which start the whole process?

Which STM32, btw? The newer ones have extra features on timer, maybe useful.

JW

[Uwe Bonnes]

Okay, here with the list above more explicit. Output is open-drain, external pulled up. Second channel is connected to first channel either internal or external.

• Arm timer ->Output is inactive
• Start timer by setting CEN -> Output gets active
• Compare register triggers -> Output gets inactive
• Other channel waiting for Rising edge
• ARR triggers after guard period: Timer stops _and_ Output stays inactive

 The code is in common code for handling Onewire in Ethernut https://sourceforge.net/p/ethernut/code/HEAD/tree/trunk/nut/arch/cm3/dev/stm/stm32_owitim.c (OwiTimerStart).

It should run on any STM32 best, but if any newer STM could do without having to disable IRQs, conditional code could be added.

[waclawek.jan]

Sorry, I'm not going to read hundreds of lines of code.

What is "arm timer" (first step)? Some software process or hardware stimulus? If software, are there timing constraints? If hardware, external signal, or some internal source (timer, DMA)?

How is CEN set, "manually" (by software), or by hardware, through trigger mode of the slave-mode controller? Again, external signal, or internal from another timer?

In the "traditional" timer and PWM mode, AFAIK, one of the edges is ALWAYS at the moment of CNT transitioning between ARR->0.

In the newer timers which have Asymmetric/Combined PWM modes ('L4, 'F7, 'H and presumably 'G) , you can (at the cost of two channels) generate a pulse which is not aligned to the overflow. So, here, you'd set it so that the pulse starts at the 0->1 transition, and then stop on any other moment within ARR, and this would not generate an edge at the ARR->0 transition.

Can this library be made generic, i.e. with no dependency on Ethernut or particular hardware? If time permits, I am willing to cooperate in something which can be used generally.

JW

[Uwe Bonnes]

Jan,

no need to experiment for you. My question was if, I overlook some timer mode, that does what I want. In short, it would be Timer Output gated by hardware with CEN.

Just to translate the OwiTimerStart() code more generic

• Set up registers
• Generate Update event by the Event generation register
• Global disable interrupts
• Set PWM mode 5: Force active level
• Set PWM mode 2: Set channel 1 to inactive level on match.
• Start Timer by setting TIM_CR_CEN
• Allow global interrupts