STM32, 'simple' issue of changing IRQ priorities (!)

[markaren1]

Posted on June 02, 2012 at 18:46

Hi All,

Is there an easy way to change the priority of TMR1interrupt ? I need to change it so that it has lower priority than USART1, 2 & 3.

The M3 TRM, while being quite comprehensive appears (to my simple mind) almost unreadable. ''Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest''.

Yup, got that, but within the STM32, TMR1 is located at position 24, priority 31, how does that relate to a priority table with 32 x 8 bit entries ?

I am sure someone must have written an idiots-guide to this question.

Anyway, any help much appreciated.

Thanks,

Mark

[markaren1]

Posted on June 02, 2012 at 19:36

Ahaah, looks like I have been looking in the wrong place...

PM0056 seems to be quite enlightening

From: ather.m

Posted: Saturday, June 02, 2012 6:46 PM

Subject: STM32, 'simple' issue of changing IRQ priorities (!)

Hi All,

Is there an easy way to change the priority of TMR1interrupt ? I need to change it so that it has lower priority than USART1, 2 & 3.

The M3 TRM, while being quite comprehensive appears (to my simple mind) almost unreadable. ''Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest''.

Yup, got that, but within the STM32, TMR1 is located at position 24, priority 31, how does that relate to a priority table with 32 x 8 bit entries ?

I am sure someone must have written an idiots-guide to this question.

Anyway, any help much appreciated.

Thanks,

Mark

[Tesla DeLorean]

Posted on June 03, 2012 at 14:33

I'd certainly recommend Joseph Yiu's Cortex M3 book, this may give a dry coverage than the technical reference manuals.

The take away with the STM32F1 implementation is that each interrupt has a 4-bit field associated with it, that you program along with the service routine address, that defines the priority/preemption level of that interrupt. The interrupt vector number only plays a part when you set two interrupts with identical settings.

The functions you want to look at are NVIC_Init(), and NVIC_GroupPriorityConfig().

[mehmet.karakaya]

Posted on June 03, 2012 at 23:37

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/TIM2 encoder mode - please help !&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=882

here an answer to your question

[markaren1]

Posted on June 04, 2012 at 20:09

Thanks for your comments guys...

I finally found everything that I needed, and in summary I was taking the ARM docs too literally.

The codesourcery tool chain defines a structure ''NVIC_type'', that contains U8 elements IP[240]. This ties up with the ST data sheet quite well.

The ARM doc DDI 0337E (page 8-16) shows the Interrupt Priority Registers as an array of 8 x U32s, broken into 4 x U8s each -- this is apparently not to be taken literally.

This caused me more than a little bit of a headache trying to figure out what was going on.

ST simply threw the problem over the fence within their docs saying ''see the ARM docs'', this was not very elegant of them...

The solution to my problems (as always) was rather simple:

SCB->AIRCR = 0x05FA0300; // set 16 groups of priorities

NVIC->IP[25] = 0x10; // drop priority of TMR1 int

Anyway, hope that saves someone else some loss of hair.

Regards,

Mark