STM32 Interrupt Priority

[akshayamk]

Posted on January 15, 2016 at 09:16

Hello!

I am using a STM32F302 custom made board.

When I set TIM2, CAN_TX and CAN_RX at the same priority, CAN_TX and CAN_RX interfere with the performance and interrupt timer of TIM2. I checked the user manual and I noticed that TIM2 had a lower priority than the CAN interrupts.

I also tried setting a higher priority for TIM2 using the NVIC_SetPriority function but it did not help.

Is there any way I can configure such that TIM2 has higher priority so it is not affected by the CAN_TX and CAN_RX interrupts?

[Tesla DeLorean]

Posted on January 15, 2016 at 12:35

Review Cortex-M4 documentation.

NVIC Grouping, ie how the 4-bits used in the STM32 are split between Priority and Preemption.

Preemption is where it breaks into the currently running state, Priority is where it orders/sequences the execution of the next interrupt when it finishes the current one.

[akshayamk]

Posted on January 20, 2016 at 01:57

Hello Clive,

Thanks for your reply.

I changed the pre-empt and sub priorities according to the NVIC grouping that allocates the bits to pre-empt and sub priorities.

Thanks!