STM32 : execute code from SRAM

[bp_it]

Posted on November 24, 2010 at 11:02

STM32 : execute code from SRAM

[bp_it]

Posted on May 17, 2011 at 14:15

[Andrew Neil]

Posted on May 17, 2011 at 14:15

''it does'nt work''

 

What, exactly, ''doesn't work''?

In what way does it ''not work''?

''help me please''

It's hard to help when you don't say what the actual problem is!

[Tesla DeLorean]

Posted on May 17, 2011 at 14:15

There are specific requirements regarding the address used as a vector table location, and there will still need to be a primary vector table from which to boot.

You might need to modify your startup.s or crt0_gnu.s, to achieve your goals cleanly and efficiently.

[bp_it]

Posted on May 17, 2011 at 14:15

Hi clive1,

W

hat specific requirements?

[Tesla DeLorean]

Posted on May 17, 2011 at 14:15

We'll I'm pretty sure that if you are executing ANY code from FLASH (ie outside your IRQ) it's going to be stalling the pipeline in a non-interruptable way.

The quickest way to test that is to make a small foot-print demo that runs completely in RAM.

[bp_it]

Posted on May 17, 2011 at 14:15

I tried everything!

My vectors table is in SRAM, my IRQHandler is in SRAM and is executed when data arrives during the execution of FLASH_Erase but it is as if USART1 not working!

I do not know what else to try!

This is myUSART1_ IRQHandler

INRAM void INRAM_USART1_IRQHandler(void)

{

    uint16_t reg;

    if ((USART1->SR & USART_FLAG_RXNE)) {

        // Réemission de la donnée

        USART1->DR = USART1->DR;

        Test=32;

    }

    if ((USART1->SR & USART_FLAG_IDLE)) {

        // Ligne IDLE

        // Clear IT pending

        reg = USART1->SR;

        reg = USART1->DR;

        IndexRcp = ID_ADR_DST;

        EnEcoute = TRUE;

        LgLSB = FALSE;

    }

    if ((USART1->SR & USART_FLAG_LBD)) {

        // LIN BREAK detection

        // Clear IT pending

        USART1->SR &= (uint16_t)~USART_FLAG_LBD;

         // La carte est transparente, le BREAK est envoyé immédiatement

        USART1->CR1 |= CR1_SBK_Set;

        Test=33;

    }

    if ((USART1->SR & USART_FLAG_ORE)) {

        // Error interrupt

        // OverRun Error interrupt

        UARTErreur |= USART_FLAG_ORE;

        reg = USART1->SR;

        reg = USART1->DR;

    }

    if ((USART1->SR & USART_FLAG_NE)) {

        // Noise Error interrupt

        UARTErreur |= USART_FLAG_NE;

        // Clear IT pending

        reg = USART1->SR;

        reg = USART1->DR;

    }

}

[Tesla DeLorean]

Posted on May 17, 2011 at 14:15

The alignment required by the NVIC unit.

You will need to copy the entire vector table into RAM, as well as the as having the one you booted from. The IRQ routines need to be in RAM, along with any library code it calls/touches. As any access to FLASH during the write/erase functions will block processor execution.