STM32 Ethernet RMII set up issues

[cjbruff]

Hey all,

 I've been working on this issue for about a week and am still not gaining any traction. 

I am trying to set up the RMII for the STM32H723ZG eval board (I cannot use the MII as we are using the pins for other peripherals).

The LwIP TCP echo works fine with a functioning ping yet I still have not been able to configure it correctly. Any help is greatly appreciated. 

(tutorials followed at the end of the post and screen shots below.)

 

 

 

 

 

 

 

 

I followed the following tutorials:
 https://elektronika327.blogspot.com/p/stm32.html

https://controllerstech.com/stm32-ethernet-1-connection/

https://community.st.com/t5/embedded-software-mcus/how-to-make-ethernet-and-lwip-working-on-stm32/td-p/261456

https://www.reddit.com/r/embedded/comments/13rcrqf/stm32h723zg_creating_tcpip_with_lwip_but_cannot/

https://www.mathworks.com/help/supportpkg/stmicroelectronicsstm32f4discovery/ug/ethernet-options.html

 

 

[LCE]

> The LwIP TCP echo works fine with a functioning ping yet I still have not been able to configure it correctly. Any help is greatly appreciated. 

If that is working then your RMII (which is the hardware interface to the PHY) is set up correctly.

So what is your problem?

[cjbruff]

So it is working with the example, but when I follow the tutorial it does not work.

 

I also downloaded and built the .ioc file from the stm hotstop git hub(attached) but to no avail.

https://github.com/stm32-hotspot/STM32H7-LwIP-Examples/blob/main/STM32H723_Nucleo_ETH/STM32H723_Nucleo_ETH.ioc

[Pavel A.]

The last one should work. Does it ping? Could you elaborate what exactly is not good? 

[cjbruff]

The issue was with the HEAP pointer for the LWIP.

I was assigning 0x24000000 to ETH when this address should have been used for the LWIP heap.

 

[LCE]

Ah, the memory areas in H7... :D

My linker file looks like this now, for an application basically audio/SAI/I2S -> OCTOSPI -> ETH with lwIP, with lots of "__attribute__((section(".xyzSection")))" in the source code :

/* Specify the memory areas */
MEMORY
{
	ITCMRAM	(xrw): ORIGIN 	= 0x00000000,	LENGTH = 64K
	FLASH 	 (rx): ORIGIN 	= 0x08000000,	LENGTH = 1024K
/* DTCM: 128 kB
 *	0x2000 0000 - 0x2001FFFF
 *	used as "general" RAM
 *	!!! no DMA access !!!
 */
	DTCM_HPST(xrw)		: ORIGIN = 0x20000000, LENGTH = 5K			/* DTCM heap & stack */
	DTCM_NOINIT(xrw)	: ORIGIN = 0x20001400, LENGTH = 1K			/* DTCM no init */
	DTCMRAM(xrw)		: ORIGIN = 0x20001800, LENGTH = 122K		/* DTCM */

	SRAXI_D1(xrw)		: ORIGIN = 0x24000000, LENGTH = 128K
	SRAXI_D1_LWIP(xrw)	: ORIGIN = 0x24020000, LENGTH = 128K
	SRAXI_D1_A2IP(xrw)	: ORIGIN = 0x24040000, LENGTH = 64K

	SRAM1_D2(xrw)		: ORIGIN = 0x30000000, LENGTH = 16K
	SRAM2_D2(xrw)		: ORIGIN = 0x30004000, LENGTH = 16K

	SRAM4_D3(xrw)		: ORIGIN = 0x38000000, LENGTH = 16K			/* only D3 access */

	OSPI2_D1(xrw)		: ORIGIN = 0x70000000, LENGTH = 0x1000000		/* OCTOSPI 2 */
}

 Setting this up reminded me a lot of FPGA programming with local constraints (manually placing some logic units, to make sure the Place & Route algorithm gets the timing done).