STM32 Controller need Hard Reset after power on to start Booting

[Dhvanish Parekh]

Posted on December 29, 2017 at 06:08

Hi All,

I am using the STM32L476 series controller in one of my projects. It is working as expected for all interfaces connected. But we are facing an issue of self-boot here.

We have observed following things during debugging:

1. The controller starts booting after power ON/OFF sequence when it is connected with ST-Link debugger.
2. As soon as I remove debugger and do ON/OFF sequence it fails to start booting process. Everytime we have to provide the manual reset to the controller to start booting.
3. Out of 10 ON/OFF sequence, Controller hardly starts booting in 2 random times.
4. Here I have also tried connecting BOOT0 pin with GND through 10K resistor.

For your reference, I have attached its schematic.

Let me know if any other details required.

Thanks,

Dhvanish Parekh 

#power-on-reset #stm32

[Tesla DeLorean]

Posted on December 31, 2017 at 14:40

Can't see attachments in the current views workable in the forum.

Part might be starting but could be stuck in Hard Fault Handler, Error_Handler() or other while(1) loops strategically dumped throughout your code.

For testing without a debugger the use of a serial port for debug/telemetry data is recommended. Use that to output progress information or identify error/fault conditions, like the external clocks not starting, etc. You could also use GPIO/LED to indicate check-points in the code if you find that simpler to execute.

Use the MSI to run the part to see if that executes normally, ie don't start or change clocks, or use PLL, to establish a base line of functionality. If that works then focus on the clock set up code, and fix/instrument that.

[T J]

Posted on January 01, 2018 at 23:16

I always use a reset chip..

I never have reset or brownout issues.

[Tesla DeLorean]

Posted on January 02, 2018 at 00:23

Would agree, best to use POR circuit on any synchronous design (MCU, FPGA, etc).

Especially useful when supplies take a long time to rise, chips which can run (in the semi viable sense) at really low voltages with respect to final rail voltage, and when there are multiple supplies/rails.

[Dhvanish Parekh]

Posted on January 02, 2018 at 06:08

Hi Clive,

Kindly find below image of Schematic...

Kindly note that I have externally connected GND through 10K resistor with BOOT0 pin for boot mode setup.

[Dhvanish Parekh]

Posted on January 04, 2018 at 05:47

Hi All,

Resolved issue by externally putting high value capacitor (10uF) on NRST pin.

Thank you Clive & TJ for your kind help.

While doing debugging as you suggested, we found that delay is not sufficient between VCC & PoR. So to increase delay added high value capacitor on NRST.

Thanks,

Dhvanish Parekh