STM32 CAN bus ''bit dominant error'' meaning

[Taylor.Sean]

Posted on March 23, 2018 at 17:15

I understand a high speed CAN bus bit error means that while I am transmitting a bit outside of the arbitration period I sense the opposite bit on the bus.   However STM gives two bit errors: 'bit dominant error' and 'bit recessive error', and I'm not sure what they each mean:

Does 'bit dominant error' mean 'While I was transmitting a dominant bit the bus was sensed as recessive'   or does it mean 'While I was transmitting a recessive bit the bus was sensed as dominant' ?

Thanks

[Taylor.Sean]

Posted on March 23, 2018 at 17:30

I may have found the answer by experiment:

Shorting the CAN-H and CAN-L causes a bit dominant error - implying the meaning is

bit dominant error  =  'while transmitting a dominant bit the receiver sensed a recessive bit'.

bit recessive error  =  'while transmitting a recessive bit the receiver sensed a dominant bit'

[Tesla DeLorean]

Posted on March 23, 2018 at 18:06

Actually I think means some else's dominant bit dominates yours.

[Taylor.Sean]

Posted on March 23, 2018 at 21:36

I think the opposite - but just based on experimental observation.   A shorted CAN bus would have 0 differential voltage which would appear as a recessive bit to someone observing the bus, and I find if I short the CAN bus I see '

bit dominant error', which implies that the error is telling me that when I tried to transmit a dominant bit I read a recessive bit.

In fact I have not seen any 'bit recessive errors' in any of our 50k + deployed devices - which makes sense because if electrically the bus is screwed up to override your recessive bit transmissions I think you'd never make it past bus arbitration to where you could register a bit error.

In any case, in case anyone is interested 'bit dominant error' is, among other things, a sign that you might have (intermittent) short circuits between the CAN-H and CAN-L.   

On the other hand if CAN-H or CAN-L go open circuit I see 'stuff' and 'form' errors.

[Tesla DeLorean]

Posted on March 24, 2018 at 01:16

The STM32 applies a state via CAN_TX, and observes the bus state on CAN_RX.

Multiple devices can drive the bus and the protocol is designed so you can see if you lost to a device with a more important message ID. The loser backs off.