STM32 Bus Matrix behavior and arbitration mechanism
Hi,
I'm trying to learn DMA in depth, but I'm confused at some points. It's about Bus Matrix and Arbitration mechanism.
In STM32F446RE, there are 2 DMA controller and each one has 1 peripheral bus and 1 memory bus. Question is not about memory bus of DMA. I know if CPU and DMA tries to reach memory on same bus at same time, there is some procedure to manage arbitration on Bus Matrix. On the below Bus Matrix Block Diagram, it seems clear.
But if DMA2 reaches any APB1 peripherals directly using DMA peripheral Bus, and same time CPU is using APB1 bus to do another work on AHB Peripheral Bus 1, what happens? The CPU and DMA may even want to access the same peripheral using this way but not necessarily. Even if DMA don't have to use AHB Peripheral Bus 1, both Masters will eventually use the same bus, APB1. As i understood, there is not any arbitration mechanism because there are not overlaps on Bus Matrix. In this situation, can CPU and DMA work at same time? Is there any arbitration mehanism ?
Thans for replys.
