SRAM with less adress bits - STM32F407IG

[netogodoy]

Posted on April 18, 2012 at 19:25

Hello,

I'm developing a data acquisition system for a Formula SAE team and the electronic module that I'm designing has a FPGA to acquire multiple digital signals in parallel.

The ideia to read the data stored in the FPGA was to make it look like a SRAM memory, it would have the same functionality and some control and adress bits.

I would like to use the FSMC in SRAM mode with 8 or 16 bits of data and only 3 or 4 bits of adress. Also, I would like to use the other adress bits with other peripherals.

The solution that I came up is to only connect the adress pins that I want to use to the FSMC peripheral and leave the other pins unconnected.

For example, only the [3:0] adress pins would be actually used as adress pins. The [25:4] pins would be internally unconnected to FSMC, but connected to other peripheral of my choice.

Am I missing something or there is no problem with this ideia ?

Thanks and sorry for the bad english!

[Tesla DeLorean]

Posted on April 18, 2012 at 20:37

Classically you'd just use the high order address bits to drive a decoder which would subdivide the address space and generate CS signals for your associated peripherals/memories.

How you achieve that within the FSMC address space is up to you.

Connect three higher order address bits to the modern day equivalent to the 74LS138 type device. Say A[10..12], giving you eight 1024 byte windows.

[jlchoobs]

Posted on April 18, 2012 at 20:48

If you are saying that you only want 4 Address Bits - then this only gives you 16 Memory locations to communicatde to your FPGA - is this what you want ?

I believe if you do not assign the Alternate Function to the remaining 21 Address Bits - then they would still funcion as normal GPIOs.

If you have multiple Memory Devices than you can follow clive's example - or use multiple Chip Select Pins.

[netogodoy]

Posted on April 18, 2012 at 20:49

But there is no problem in not connecting somes pins, say A[20:5], to the FSMC and using then for other porpouse like Timers, Usart, etc ?

Thank you for you answer and suggestion! I will consider it in my design.

[frankmeyer9]

Posted on April 18, 2012 at 21:09

Assuming I understood what you want, I'm not sure if this is possible. Actually, I would be surprised.

3 or 4 address line just make up for 8 or 16 words - not actually a lot of RAM. Sounds more like a shared-memory interface.

Why not using SPI or I2C instead ?

[netogodoy]

Posted on April 18, 2012 at 21:14

That's exactly what I want, jlc.jlsilicon. [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/SRAM with less adress bits - STM32F407IG&currentviews=8]

Imagine that in my FPGA there will be 5 hardwares measuringdigitals signals in parallel and each one of then store this value in a dedicated register, and that this FPGA is (besides being a FPGA) an SRAM chip.Just for clarification, 4 hardwares will be measuring wheelspeeds and one is dedicated to the engine RPM.

When my STM32F4 needs the data measured by the FPGA, it will acess theses registers inside as if they were a memory location of one SRAM chip. Since there is only 5 memory locations I only need 3bits of adress.

Why I'm doing this ? To avoid the need to build a ''memory acess protocol'' inside my C code, where I would need to control all the signals. This way I only need to read a memory location and the FSMC will handle all the low level acess for me.

But if I use all the adress pins (without the capability of ignoring some pins), some peripherals or GPIO's needed for the project will be lost.

That's why I asked if I can just not connect via C code (Alternate Function) the pins to FSMC controller inside the chip.

[Tesla DeLorean]

Posted on April 18, 2012 at 21:29

You do not need to commit unused address pins to the AF-FSMC interface, they will just act line GPIO pins if you configure them as such. The AF unit is a pin mux.

There is no magic to accessing the FSMC space, you just read/write to it like any other memory area. You have to configure it suitably, and set the timings properly, and consider the delay your external decode might add. Put the decoder logic in the FPGA.

You could use the separate banks to generate chip selects, or you could sub-divide one of the banks into multiple peripherals, say if you needed eight.

uint8 *uart1 = (uint8 *)0x60000000;

uint8 *uart2 = (uint8 *)0x60000400;

uint8 *fpga1 = (uint8 *)0x60000800;

uint8 *fpga2 = (uint8 *)0x60001000;

fpga1[8] = 0xAA;

fpga2[6] = 0x55;

[netogodoy]

Posted on April 18, 2012 at 22:00

Thanks a lot for all the help!

Answering the user ''fm'': The FSMC is the primary option because all the ease of use it generates as clive1 and I state in our posts. 

BUT, there is one SPI and I2C reserved as a backup plan. I'm using a non-volatile FPGA (Spartan 3AN) with only 50K gates and I can't know for certain if the 5 hardwares plus the I2C or SPI core will fit in.

Another solution would be use a higher gate count FPGA, but all the others non-volatile use the ball grid package wich is a problem for me. A third solution is to use a normal FPGA with 200K or 400K gates, but then I will need to come up with a way for programming the chip every time the electronics wake up, wich is another problem because this is an embedded application.

[raptorhal2]

Posted on April 18, 2012 at 22:00

There is a much simpler way. Connect your RPM and wheel speed signals to timer capture compare inputs.

There are also commercially available data recorders for race cars. They have already solved all the problems you are going to encounter, and they have mature PC software to download and display the results. Not as much fun as doing it yourself, but theirs can be available for use much sooner than yours.

Cheers, Hal

[netogodoy]

Posted on April 19, 2012 at 05:07

Hi baird.hal.001!

There is this option too. The FPGA is connected in a way that I can re-route the signals directly to the 5 timer needed. But I want to avoid using the ARM's timers because there is a lot more going on for the STM32 to handle. Some of the things that I'm going to use: 4xUSART, 1xCAN, 1xI2C, 2x SPI, 12 ADC Channels and Ethernet. 

I agree with you that there is a wide variety of modules with plug and play features that could do a lot more with much less headache, but here in Brazil this modules are VERY expensive and the team can't afford one. So, I'm designing one and using this process as my graduation project.

 

[jlchoobs]

Posted on April 19, 2012 at 05:56

Like your idea - good as a class Project - new and creative.

Works like an UART ASIC Chip - simple to use and modular.

And, it leaves the design to use the FPGA for other /and change to other functions too.

You might want to leave a few extra pins as addresses to the FPGA - to allow parallel functionalities on the FPGA - multiple functions from the FPGA via different Addresses. 

Or, is this your plan already ? 

What FPGA are you using ?  If it is Xilinx then you can use the Stm32 to dump the Binary code to the FPGA via I2C, instead of using an additional Seeprom chip.

- How is the weather down there ? - I miss Joinville and Sao Paulo - beautiful places in the world - would like to have a summer house there.