SPI with non standard clk cycles.

[Andrew C]

Is there a way to have spi just send an abnormal number of clock cycles as opposed to just 8 cycles at a time? Is bit banging the only way? Can the LL library be configured or coded to do such a thing?

[waclawek.jan]

Some newer STM32 allow anyting between 4 and 16 bits.

JW

[S.Ma]

Yep, actually played with it for fun to try to generate SWD type bitstreams joggling with 8, 6 and 9 bits.

You can choose chunks of 4 to 16 bit. As long as the chunk size is the same, you can poll the FIFO TX level to preload next chunk without delays in transmission which will be only needed when you change gears (bit size)

[PBU]

Hi,

I am using HAL Library. I need to send 9 bits using SPI. I have configure the SPI with 9 bit data length. While sending the 9 bit data were clocked out for the first time alone, if i transfer second time it had clock out 8 bits only. Give me a suggestion to solve this issue.

Thanks

[waclawek.jan]

https://community.st.com/s/question/0D50X0000AaYTHXSQ4/sending-9-bit-data-using-spi-stm32f7