Posted on January 29, 2017 at 23:16Huh.
Try to:
- initializemaster SPI first - otherwise the lines are floating while the slave is already initialized thus might pick up spurious clocks
- decrease speed setting in OSPEEDR - the 25MHz should be enough
- set realterm to display hex and post what's those 'incorrectly received' bytes
I admit I have no explanation why changing data transmitted by slave should matter.
Style advices:
Don't use magic constants, it's a considerable effort to decipher them. Instead, use the device header defined constants throughout. You might want to define the non-single-bit bitfield values ST don't define. E.g. I use
#define DMA_SIZE__BYTE 0
#define DMA_SIZE__HALFWORD 1
#define DMA_SIZE__WORD 2
#define DMA_PRIORITY__LOW 0
#define DMA_PRIORITY__MEDIUM 1
#define DMA_PRIORITY__HIGH 2
#define DMA_PRIORITY__VERY_HIGH 3
#define DMA_DIR__P2M 0
#define DMA_DIR__M2P 1
[...]
DMA1_Channel3->CMAR = (uint32_t)redLedTable;
DMA1_Channel3->CPAR = (uint32_t)&LPTIM1->CMP;
DMA1_Channel3->CNDTR = sizeof(redLedTable) / sizeof(redLedTable[0]);
DMA1_Channel3->CCR = 0
| ( 1 * DMA_CCR_EN ) // Channel enable
| ( 0 * DMA_CCR_TCIE ) // Transfer complete interrupt enable
| ( 0 * DMA_CCR_HTIE ) // Half Transfer interrupt enable
| ( 0 * DMA_CCR_TEIE ) // Transfer error interrupt enable
| ( DMA_DIR__M2P * DMA_CCR_DIR ) // Data transfer direction
| ( 1 * DMA_CCR_CIRC ) // Circular mode
| ( 0 * DMA_CCR_PINC ) // Peripheral increment mode
| ( 1 * DMA_CCR_MINC ) // Memory increment mode
| ( DMA_SIZE__HALFWORD * DMA_CCR_PSIZE_0 ) // PSIZE[1:0] bits (Peripheral size)
| ( DMA_SIZE__HALFWORD * DMA_CCR_MSIZE_0 ) // MSIZE[1:0] bits (Memory size)
| ( DMA_PRIORITY__LOW * DMA_CCR_PL_0 ) // PL[1:0] bits(Channel Priority level)
| ( 0 * DMA_CCR_MEM2MEM ) // Memory to memory mode
;
You get the point.
Don't do anything which would hold up ISR, here, USART transmission.
JW
