SPI raise/fall time

[bpacan]

Posted on February 10, 2014 at 10:39

Hi

I'm using STM32F373x SPI in slave mode. I get errors in about 0.1% bits transmitted, occurs in 50% of units from first production series of custom board. SPI lines have RC filter installed to improve EMC immunity. Rise/fall times are about 1us with filters and 10ns without them. I get no errors without filters. My question is what parameter do I exceeded?

Table 58 defines max. rise/fall 8ns (I guess only for master, cause load is also described). I think I'm not getting out of 30-70% duty cycle. Speed is 190kHz, reducing to 80kHz didn't changed anything.

#eye-pattern #stm32-spi

[bpacan]

Posted on February 13, 2014 at 14:39

BTW I used similar SPI with board to board connection in older projects without problems (different uC). Now I checked details and it looks like Atmel AVR has much different (better for my purposes) Slave hardware, including clock sampling and max. Slave slope allowed 1.6us.